CS150 Week 2, Lecture 1Covers:1) Memory2) S-R Latch3) Level sensitive latch ( Clocked S-R Latch )4) JK Latches1) MemoryCircuits:Timing:???? Note: For 30 MHz 0.5ns transistors ( gate delays ). 2) S-R Latch Note: __Output: A0 (Zero)Input: ALD__LD__LDLDLD 0 1__LD 1 0EN (Enable)A B C DIf S=0 and R=0 thencircuit is just:SRS-R Latch:A 1 0B 1 0C 1 0D 1 0TimeOne gate delayR = 1 Q = 0 R = 1 Q = ??S = 1 Q = 0 S = 1 Q = ??S-R Latch rewritten:Illegal transitions…Cycles without change in input values.Therefore: 11 not allowed as an input.S-R Latch with NAND gates: S-R Latch with NOR gates. Bubble pushR 1 0S 1 0Q 1_ 0Q 1 0TimeOne gate delay Q R_ Q S Q R_ Q S 0 1 S 00 R 0 1 0 0 0 0 1 0 1 0 Q R_ Q S Q R_ Q S_ Q _ R_ Q _ S3) Level sensitive latch ( Clocked S-R Latch ) Unclocked S-R Latch ( Notation slightly different in Katz ) Same thing as: Enable S Q S Q _ _ R Q R Q Enable CLK4) JK Latches Q R_ Q SCLKS Q _R Q R SEnableS Q _R QS Q _R QS R Q Q+0 0 0 0 HOLD 0 0 1 1 0 1 0 0 RESET0 1 1 0 1 0 0 1 SET1 0 1 1 1 1 0 ? FORBIDDEN1 1 1 ? S Q _R QS R Q Q+* * 0 Q0 0 1 Q 0 1 1 0 1 0 1 1 1 1 1 ? S Q _R Q J KJ K Q+0 0 Q 0 1 0 1 0 1 _1 1 Toggle ( Q )S Q _R Q J KJ Q _K QJ: Jam a 1 into Q K: Klear value in Q
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