Hardware Description Languages Verilog Verilog Structural Models Combinational Behavioral Models Syntax Examples CS 150 Spring 2007 Lecture 4 Verilog 1 Quick History of HDLs ISP circa 1977 research project at CMU Abel circa 1983 developed by Data I O Targeted to programmable logic devices Not good for much more than state machines Verilog circa 1985 developed by Gateway now Cadence Simulation but no synthesis Similar to Pascal and C Delays is only interaction with simulator Fairly efficient and easy to write IEEE standard VHDL circa 1987 DoD sponsored standard Similar to Ada emphasis on re use and maintainability Simulation semantics visible Very general but verbose IEEE standard CS 150 Spring 2007 Lecture 4 Verilog 2 Design Methodology Structure and Function Behavior of a Design HDL Specification Simulation Synthesis Verification Design Behave as Required Functional I O Behavior Register Level Architectural Logic Level Gates Transistor Level Electrical Timing Waveform Behavior Generation Map Specification to Implementation CS 150 Spring 2007 Lecture 4 Verilog 3 Verilog VHDL The standard languages Very similar Many tools provide front ends to both Verilog is simpler Less syntax fewer constructs VHDL supports large complex systems Better support for modularization More grungy details Hello world is much bigger in VHDL CS 150 Spring 2007 Lecture 4 Verilog 4 Verilog Supports structural and behavioral descriptions Structural Explicit structure of the circuit How a module is composed as an interconnection of more primitive modules components E g each logic gate instantiated and connected to others Behavioral Program describes input output behavior of circuit Many structural implementations could have same behavior E g different implementations of one Boolean function CS 150 Spring 2007 Lecture 4 Verilog 5 Verilog Introduction the module describes a component in the circuit Two ways to describe Structural Verilog List of components and how they are connected Just like schematics but using text Hard to write hard to decode Useful if you don t have integrated design tools Behavioral Verilog Describe what a component does not how it does it Synthesized into a circuit that has this behavior CS 150 Spring 2007 Lecture 4 Verilog 6 Structural Model Composition of primitive gates to form more complex module Note use of wire declaration module xor gate out a b By default identifiers input a b are wires output out wire abar bbar t1 t2 inverter inverter and gate and gate or gate invA abar a invB bbar b and1 t1 a bbar and2 t2 b abar or1 out t1 t2 endmodule CS 150 Spring 2007 Lecture 4 Verilog 7 Structural Model Example of full adder module full addr A B Cin S Cout input A B Cin output S Cout Behavior assign Cout S A B Cin endmodule module adder4 A B Cin S Cout input 3 0 A B input Cin output 3 0 S output Cout wire C1 C2 C3 full addr full addr full addr full addr endmodule fa0 fa1 fa2 fa3 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 Cin C1 C2 C3 S 0 S 1 S 2 S 3 CS 150 Spring 2007 Lecture 4 Verilog 8 Structural C1 C2 C3 Cout Simple Behavioral Model Combinational logic Describe output as a function of inputs Note use of assign keyword continuous assignment module and gate out in1 in2 input in1 in2 Output port of a primitive must output out be first in the list of ports assign out in1 in2 Restriction does not apply to modules endmodule CS 150 Spring 2007 Lecture 4 Verilog 9 Verilog Module Corresponds to a circuit component Parameter list is the list of external connections aka ports Ports are declared input output or inout inout ports used on tri state buses Port declarations imply that the variables are wires module name ports module full addr A B Cin S Cout input A B Cin output S Cout assign Cout S A B Cin endmodule CS 150 Spring 2007 Lecture 4 Verilog 14 inputs outputs Verilog Continuous Assignment Assignment is continuously evaluated assign corresponds to a connection or a simple component with the described function Target is NEVER a reg variable use of Boolean operators for bit wise for logical negation assign A X Y Z bits can take on four values 0 1 X Z assign B 3 0 4 b01XX assign C 15 0 16 h00ff variables can be n bits wide MSB LSB assign 3 Cout S 3 0 A 3 0 B 3 0 Cin use of arithmetic operator multiple assignment concatenation delay of performing computation only used by simulator not synthesis CS 150 Spring 2007 Lecture 4 Verilog 15 Comparator Example module Compare1 A B Equal Alarger Blarger input A B output Equal Alarger Blarger assign Equal A B A B assign Alarger A B assign Blarger A B endmodule CS 150 Spring 2007 Lecture 4 Verilog 16 Comparator Example Make a 4 bit comparator from 4 x 1 bit comparators module Compare4 A4 B4 Equal Alarger Blarger input 3 0 A4 B4 output Equal Alarger Blarger wire e0 e1 e2 e3 Al0 Al1 Al2 Al3 B10 Bl1 Bl2 Bl3 Compare1 Compare1 Compare1 Compare1 cp0 A4 0 cp1 A4 1 cp2 A4 2 cp3 A4 3 B4 0 B4 1 B4 2 B4 3 e0 e1 e2 e3 assign Equal e0 e1 e2 assign Alarger Al3 Al2 Al1 e3 Al0 e3 assign Blarger Alarger endmodule Al0 Al1 Al2 Al3 Bl0 Bl1 Bl2 Bl3 e3 e3 e2 e2 e1 Equal CS 150 Spring 2007 Lecture 4 Verilog 17 Announcements Lecture room change EFFECTIVE 1 FEB 07 Beware of what you ask for 159 Mulford Hall near West Gate Oxford Street Card Key Access to 125 Cory You can t get it until 7 February For access EECS Keys Cardkeys Copy Cards Assistant Loretta Lutcher 253 Cory 642 1527 loret eecs Loretta issues keys and electronic cardkeys for Cory Hall Handles cardkey problems She can add 125 Cory to your Cal Card CS 150 Spring 2007 Lecture 4 Verilog 18 Simple Behavioral Model the always block always block Always waiting for a change to a trigger signal Then executes the body module and gate out in1 in2 input in1 in2 output out reg out always in1 or in2 begin out in1 in2 end endmodule Not a real register A Verilog register Needed because of assignment in always block Specifies when block is executed I e triggered by which signals CS 150 Spring 2007 Lecture 4 Verilog 19 always Block Procedure that describes the function of a circuit Can contain many statements including if for while case Statements in the always block are executed sequentially Continuous assignments are executed in parallel Entire block is executed at once Final result describes the function of the circuit for current set of inputs intermediate assignments don t matter only the final result begin end used to group statements CS 150 Spring 2007 Lecture 4 Verilog 20 Complete Assignments If an always block executes and a variable is
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