Fall 2002 EECS150 - Lec11-cl1Page 1EECS150 - Digital DesignLecture 11 - Combinational Logic Circuits Part 1 - AddersOctober 1, 2002John WawrzynekFall 2002 EECS150 - Lec11-cl1Page 2AddersFull-adder cell (FA) revisited:FAa bcincout sa b cin cout s0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 100 01 11 10 00 01 11 100101ab abcin cincoutsFall 2002 EECS150 - Lec11-cl1Page 3Carry-ripple Adder• Each cell:ri=aiXOR biXOR cincout=aicin+aibi+bicin=cin(ai+ bi) + aibi• 4-bit adder:• What about subtraction?“Full adder cell”Fall 2002 EECS150 - Lec11-cl1Page 4SubtractorsA - B = A + (-B)How do we form -B?1. complement B 2. add 1SUBs0s1sn-1bn-1 b1 b0an-1 a1 a0cout cinn-bit adderFall 2002 EECS150 - Lec11-cl1Page 5Delay in Ripple Adders• Ripple delay amount is a function of the data inputs:• However, we usually only worry about the worst case delay on the critical path. There is always at least one set of input data that exposes the worst case delay.1 0 0 1 0 11 00 0 0 01 0 1 0 1 11 00 0 0 01 0 1 0 1 11 00 0 0 11 0 1 0 1 11 00 0 1 1t0t1t2t3Fall 2002 EECS150 - Lec11-cl1Page 6Adders (cont.)Ripple AdderRipple adder is inherently slow because, in generals7 must wait for c7 which must wait for c6 …T α n, Cost α nHow do we make it faster, perhaps with more cost?FAc0a0b0s0c1c2c3c4c5c6c7s7 s6Fall 2002 EECS150 - Lec11-cl1Page 7Carry Select AdderFAc0a0b0s0FA1 0 1 01 0 1 001c810a1a2a3a4a5a6a7a4a5a6a7b7 b6 b5 b4 b3b7 b6 b5 b4b2 b1s1s2s3s4s5s6s7T = Tripple_adder/ 2 + TMUXCOST = 1.5 * COSTripple_adder+ (n+1) * COSTMUXFall 2002 EECS150 - Lec11-cl1Page 8Carry Select Adder• Extending Carry-select to multiple blocks• What is the optimal # of blocks and # of bits/block?– If # blocks too large delay dominated by total mux delay– If # blocks too small delay dominated by adder delay101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder4-bit Addera3-a0b3-b0cincouta11-a8b11-b8a15-a12b15-b12 b7-b4 a7-a4bits N of stages NT α sqrt(N),Cost ≈2*ripple + muxesFall 2002 EECS150 - Lec11-cl1Page 9Carry Select Adder•Ttotal= sqrt(N) TFA– assuming TFA= TMUX• For ripple adder Ttotal= N TFA• Is sqrt(N) really the optimum?– From right to left increase size of each block to better match delays– Ex: 64-bit adder, use block sizes [13 12 11 10 9 8 7]• How about recursively defined carry select?101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder4-bit Addera3-a0b3-b0cincouta11-a8b11-b8a15-a12b15-b12 b7-b4 a7-a4Fall 2002 EECS150 - Lec11-cl1Page 10Carry Look-ahead Adders• In general, for n-bit addition best we can achieve is delay α log(n)• How do we arrange this? (think trees)• First, reformulate basic adder stage:carry “kill” ki= ai’bi’carry “propagate” pi= ai⊕ bicarry “generate” gi= aibici+1= gi+ picisi= pi⊕ ci0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b cici+1sFall 2002 EECS150 - Lec11-cl1Page 11Carry Look-ahead Adders• Ripple adder using p and g signals:• So far, no advantage over ripple adder: T α Np0g0s0= p0⊕ c0c1= g0+ p0c0s0a0b0p1g1s0= p1⊕ c1c2= g1+ p1c1s1a1b1p2g2s2= p2⊕ c2c3= g2+ p2c2s2a2b2p3g3s3= p3⊕ c3c4= g3+ p3c3s3a3b3c0c4Fall 2002 EECS150 - Lec11-cl1Page 12Carry Look-ahead Adders• Expand carries:c0 c1= g0+ p0c0c2= g1+ p1c1= g1+ p1g0+ p1p0c0c3= g2+ p2c2= g2+ p2g1+ p1p2g0+ p2p1p0c0c4= g3+ p3c3= g3+ p3g2+ p3p2g1+ . . ....• Why not implement these equations directly to avoid ripple delay?– Lots of gates. Redundancies (full tree for each).– Gate with high # of inputs.• Let’s reorganize the equations.Fall 2002 EECS150 - Lec11-cl1Page 13Carry Look-ahead Adders• “Group” propagate and generate signals:• P true if the group as a whole propagates a carry to cout• G true if the group as a whole generates a carry• Group P and G can be generated hierarchically.pigipi+1gi+1pi+kgi+kP = pipi+1… pi+kG = gi+k+ pi+kgi+k-1+ … + (pi+1pi+2… pi+k)gicincoutCout = G + PCinFall 2002 EECS150 - Lec11-cl1Page 14Carry Look-ahead Addersa0b0a1b1a2b2aa3b3a4b4a5b5bc3= Ga+ Pac0PaGaPbGba6b6a7b7a8b8cc6= Gb+ Pbc3PcGcP = PaPbPcG = Gc+ PcGb+ PbPcGac9= G + Pc0c09-bit Example of hierarchically generated P and G signals:Fall 2002 EECS150 - Lec11-cl1Page 15c0a0b0s0a1b1s1c1a2b2s2a3b3s3c3c2c0c0a4b4s4a5b5s5c5a6b6s6a7b7s7c7c6c0c4c0c8p,gP,GP,GcincoutP,GPa,GaPb,GbP = PaPbG = Gb+ GaPbCout = G + cinPaibisip,gcici+1p = a ⊕ bg = abs = p ⊕ cici+1 = g + cip8-bit Carry Look-ahead AdderFall 2002 EECS150 - Lec11-cl1Page 16p0g0s0p1g1s1c1= g0+p0c0p1g2s2c2p3g3s3c3= g2+p2c2p4g4s4p5g5s5p6g6s6c6p7g7s7c0c5= g4+p4c4c7= g6+p6c6c4c2=G8+P8c0P8=p0p1G8=g1+p1g0P9=p2p3c6=Ga+Pac4Pa=p4p5Ga=g5+p5g4Pb=p6p7G9=g3+p3g2Gb=g7+p7g6c4=Gc+Pcc0Pc=P8P9Gc=G9+P9G8Pd=PaPbGd=Gb+PbGac8=Ge+Pec0Pe=PcPdGe=Gd+PdGcc0c4c88-bit Carry Look-ahead Adder with 2-input gates.Fall 2002 EECS150 - Lec11-cl1Page 17Bit-serial Adder• Addition of 2 n-bit numbers:– takes n clock cycles,– uses 1 FF, 1 FA cell, plus registers– the bit streams may come from or go to other circuits, therefore the registers are optional.• A, B, and R held in shift-registers. Shift right once per clock cycle.• Reset is asserted by controller.n-bit shift registern-bit shift registersscresetRFAFFBAFall 2002 EECS150 - Lec11-cl1Page 18Adders on the Xilinx Virtex• Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB.• The arithmetic logic includes an XOR gate and AND gate that allows a 2-bit full adder to be implemented within a slice. • Cin to Cout delay = 0.1ns, versus 0.4ns for F to X
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