EECS 150 - Components and Design Techniques for Digital SystemsLec 11 – Putting it all together…10-5-04David CullerElectrical Engineering and Computer SciencesUniversity of California, BerkeleyPresented by: Kaushik Ravindranhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150Outline• Top-to-bottom– What have we covered so far?• Combo Lock example – Hw 4– FSM to logic– Mapping to FPGAs• Counters revisited• Announcements• Another example – Ant BrainDigital design - as we’ve seen itSystem specification (in words)Datapath specificationController specificationComb. logic operationsVerilog dataflowGates / LUTsFSM generationSTT / STD / EncodingLogic: nextstate/outputsVerilog behaviorGates / LUTs / FFARTARTLec 7, 8: FSM impl.Lec 8, 9: Modeling FSMsLec 5, 6: Logic min.Lec 4: HDL, LabsLec 2, 3: CMOS, FPGALec 5, 6: Logic min.Lec 4: HDLs, LabsLec 2, 3: CMOS, FPGAWhere are we now?• (Synchronous) Sequential systems• Given datapath and control specifications– Generate comb. logic for datapath» Minimize logic for efficient implementation– Generate FSM for controller» Choose implementation, encoding» Generate logic for nextstate and output– Describe datapath and controller in Verilog» structure, dataflow and behavior» Map onto gates or LUTs• Seems like a good point to “test” your understanding!Sequential Logic Implementation• Models for representing sequential circuits– Finite-state machines (Moore and Mealy)– Representation of memory (states)– Changes in state (transitions)• Design procedure– State diagrams– Implementation choice: counters, shift registers, FSM– State transition table– State encoding– Combinational logic» Next state functions» Output functionsAbstraction of State Elements• Divide circuit into combinational logic and state• Localize feedback loops and make it easy to break cycles• Implementation of storage elements leads to various forms of sequential logic Forms of Sequential Logic• Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements)• Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock)• States: determined by possible values in sequential storage elements• Transitions: change of state• Clock: controls when state can change by controlling storage elements• Sequential Logic– Sequences through a series of states– Based on sequence of values on input signals– Clock period defines elements of sequenceFSM RepresentationsExample: FSM Design – Combo lock• Combination lock from first lecture resetopen/closednewC1 C2 C3comparatorvalueequalmultiplexerequalcontrollermuxcontrolclockdatapathController !!" #$Combo lock - controller implementation• Implementation of the controllerCombo Lock - State Encoding % % % % && % ' ' % ' ' ' ' & & % ' ( ( % ( ( ( ( && % ( ) * % % % )* )* % % % & & && % Symbolic states and outputs+ ,!'!(-.# / , ! '! (! ) * ! , ! One possible encoding Concrete encodingFSM implementation• Steps for the hardware designer:– Word specification– FSM design– Encoding– Verification!• At this point, hand over to synthesis tools:– Describe FSM behavior in Verilog– Synthesize controller • Good encoding– Better performance– Fewer state bits– Possibility of state minimization– Tools also try to figure this outFor this example, go through the logic synthesis steps (ideally, tools take care of all this)…Example: Combo Lock – Hw
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