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Time TableMotivationIntroduction to the CAD FlowDesign EntrySimulationSynthesisTranslate, Map, Place and RouteTranslateMapPlacementRoutingPlace and Route ToolsProgram HardwareVerificationPreLabLab ProcedureProject SetupFunctional SimulationSynthesisPlace and RoutePost-PAR SimulationHardware VerificationReferencesLab 1 CheckoffEECS150: Lab 1, FPGA CAD ToolsUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 Time TableASSIGNED Friday, August 29thDUE Week 3: September 7th− 13th, 10 minutes after your lab section starts2 MotivationIn this lab you will take a simple design through the FPGA Computer Aided Design (CAD) tool-flow,starting from design entry all the way to programming the hardware. This lab will give you experiencewith the software that you’ll be using for the rest of the semester.3 Introduction to the CAD FlowFigure 1 shows the general CAD tool flow to which you have access in this lab. Highlighted in bold isthe flow which we will be using.Figure 1 CAD Tool FlowXilinx ISESynplify Pro(Synthesis)Verilog HDLVHDL HDLSchematicModelSim(Siimulation)Translate, Map, PARiMPACTLogic AnalyzerChipScopeSchematic CaptureConvert to VerilogDesign EntryA design written in Verilog using Notepad is fed through Synplify Pro, the Xilinx PAR tools andfinally iMPACT which will program it into the FPGA. The whole process is described in detail below.13.1 Design EntryThe first step in logic design is to conceptualize your design. Once you have a good idea about the functionand structure of your circuit and maybe a few block diagram sketches, you can start the implementationprocess by specifying your circuit in a more formal manner.In this class we will use a Hardware Description Language (HDL) called Verilog. HDLs have severaladvantages over other methods of circuit specification:1. Ease of editing, since files can be written using any text editor2. Ease of management when dealing with large designs3. The ability to use a high-level behavioral description of a circuit.In this class we will default to using Notepad to edit Verilog. Fancier editors are available, and in factare included with the CAD tools such as Xilinx ISE and ModelSim; however these tools are slow andwill often hinder you. For this lab, we will provide you with a complete and working project in Verilog.3.2 SimulationWith a design in hand, the first step is always to test it using an HDL simulator. Because actuallyimplementing any large design can take upwards of half an hour, it is much too time consuming tosimply synthesize a design, check to see if it works and then tweak it. In fact, because a fully implementeddesign in hardware runs so quickly (at megahertz clock frequencies) and involves so many signals, even ifimplementation took a mere 30 sec, it is highly impractical to debug the final hardware implementationdirectly.To speed up the design cycle and also to provide the designer, you, with more detailed informationabout the functioning of a running circuit, we use HDL simulators such as ModelSim. Simulation allowsyou to provide specific test inputs to your circuit and observe both the outputs and the internal operationof your circuit giving you very detailed feedback as to what is happening and when.Because simulation is software rather than hardware-based, it is relatively slow taking perhaps 5 minto simulate 5 msec of real time. But it allows you to create very specific input conditions, using specialVerilog modules called “testbenches” to exercise your circuit. You can even to print out text messagesin the event of problems, rather than forcing you to look at the binary output of your circuit.3.3 SynthesisOnce a design is entered, simulated and debugged, the next step in the CAD Tool Flow is synthesis. Itis the job of the synthesis program to translate the Verilog description of the circuit into an equivalentcircuit made of primitive circuit components that can be directly implemented in an FPGA.In a way, the synthesis tool is almost like a compiler. Where a compiler translates a high levellanguage, such as C, into a sequence of primitive commands that can be directly executed on a processor,synthesis translates a high level language, in this case Verilog, into primitive circuit components that canbe directly implemented on an FPGA. The final product of a synthesis tool is a netlist file, a text filethat contains a list of all the instances of primitive components in the translated circuit and a descriptionof how they are connected. As C and Verilog are both alike in that they are high-level descriptions foryour program/design, compilation and synthesis are alike in that they translate your description into aform that a machine can more easily understand.3.4 Translate, Map, Place and RouteFrom the netlist produced by the synthesis tools, we must somehow create a file containing the bitsneeded to configure the LUTs, Flip-Flops, and other resources that make up the FPGA. This is the jobof the Translate, Map, and the Place and Route (PAR) tools.23.4.1 TranslateTranslate takes as input a netlist file from the synthesis tools and outputs a Xilinx database file, whichis the same thing as the netlist, reduced to logic elements expressed in terms that Xilinx-specific devicescan understand.3.4.2 MapMap takes as input the database file which was output from Translate and ‘maps’ it to a specific XilinxFPGA. This is necessary because different FPGAs have different architectures, resources, and compo-nents.3.4.3 PlacementPlacement takes as input the result of the “Map” step and determines exactly where, physically, on theFPGA each LUT, flip-flop, and logic gate should be placed. For example, a 4LUT implementing thefunction of a 4-input NAND gate in a netlist could be placed in any of the 38,400 4LUTs in a XilinxVirtex XCV2000E FPGA chip. Clever choice of placement will make the subsequent routing easier andresult a circuit with less delay.3.4.4 RoutingOnce the components are placed, the proper connections must be made. This step is called routing,because the tools must choose, for each signal, one of the millions of paths to get that signal from itssource to its destination.Because the number of possible paths for a given signal is very large, and there are many signals, thisis typically the most time consuming part of implementing a design, aside from specification. Planningyour design well and making it compact and efficient will significantly reduce how long this step


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