EECS 150 - Components and Design Techniques for Digital Systems Lec 27 – Summary (whirlwind) 12-9-04BackgroundCourse ContentTrick you into building an extreme projectLevels of Digital DesignWhat makes Digital Systems tick?The 150 “stuff”Combinational Logic (CL) DefinedTransistor-level Logic Circuits - NANDCombinational logic summaryTransistor-level Logic Circuits - LatchD Flip-FlopTiming MethodologiesTiming Methodologies (cont’d)What’s an FSM?Formal Design Process for FSMsComposing FSMs into larger designsSequential Synchronous Elements150 and the changing timesVirtex-E Configurable Logic Block (CLB)HDLsFinite State Machines in VerilogDesign Methodology in DetailConfiguring CLBsConfiguring RoutesTiming for Synchronous CircuitsTypical SRAM Organization: 16-word x 4-bitClassical DRAM Organization (Square)DRAM with Column bufferDigital Arithmetic2s Complement Adder/SubtractorDigital design - as we’ve seen itFinal Example: Ant Brain (Ward, MIT)Serial Line TX/RX – dealing with I/OThe GAMEComputer OrganizationDesign hierarchyDatapath vs ControlDatapath DesignArray Multiplier“Shift and Add” MultiplierDIVIDE HARDWARE Version 2Register Transfers - interconnectRegister Transfer Level DescriptionsList Processor Example3. Architecture #1Approaching an ISAInstruction SequencingInstruction ExecutionNetworking LayersWhat the PHY doesCSMAError Correction Codes (ECC)Correcting Code ConceptSECDEDConcept: Redundant CheckCRC conceptControlling Energy ConsumptionDigital DesignTraversing Digital DesignSo what’s on the final?Maintaining the Digital Abstraction (in an analog world)Moore’s Law: 2x stuff per year or soBell’s Law – new computer class per 10 yearsWhat to take away from EECS 150EECS 150 - Components and Design Techniques for Digital Systems Lec 27 – Summary (whirlwind)12-9-04 David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs15012/9/04EECS150 Lec26 - Summary2BackgroundTransfer FunctionTransistor PhysicsDevicesGatesCircuitsFlipFlopsEE 40HDLMachine OrganizationInstruction Set ArchPgm Language Asm / Machine LangCS 61CDeep Digital Design ExperienceFundamentals of Boolean LogicSynchronous CircuitsFinite State MachinesTiming & ClockingDevice Technology & ImplicationsController DesignArithmetic UnitsBus DesignEncoding, FramingTesting, DebuggingHardware ArchitectureHDL, Design Flow (CAD)12/9/04EECS150 Lec26 - Summary3Course ContentComponents and Design Techniques for Digital SystemsSynchronous Digital Hardware SystemsExample digital representation: acoustic waveformA series of numbers is used to represent the waveform, rather than a voltage or current, as in analog systems.•Synchronous: “Clocked” - all changes in the system are controlled by a global clock and happen at the same time (not asynchronous)•Digital: All inputs/outputs and internal values (signals) take on discrete values (not analog).12/9/04EECS150 Lec26 - Summary4Trick you into building an extreme project•FPGA/SDRAM provides full game logic–Court, obstructions–Moving paddles–Moving, colliding ball–All the physics•Court displayed to NTSC (TV) Video Output–Real time Sound effects ???•N64 controller (and switches) for input•How to make it multiplayer?–The network12/9/04EECS150 Lec26 - Summary5Levels of Digital Design12/9/04EECS150 Lec26 - Summary6What makes Digital Systems tick?CombinationalLogictimeclkWhat determines the systems performance?12/9/04EECS150 Lec26 - Summary7The 150 “stuff”•Building blocks of computer systems–ICs (Chips), PCBs, Chassis, Cables & Connectors•CMOS Transistors–Voltage controlled switches–Complementary forms (nmos, pmos)•Logic gates from CMOS transistors–Logic gates implement particular boolean functions»N inputs, 1 output–Serial and parallel switches–Dual structure–P-type “pull up” transmit 1–N-type •Complex gates: mux•Synchronous Sequential Elements–D FlipFlops12/9/04EECS150 Lec26 - Summary8Combinational Logic (CL) Definedyi = fi(x0 , . . . . , xn-1), where x, y are {0,1}. Y is a function of only X. •If we change X, Y will change –immediately (well almost!). –There is an implementation dependent delay from X to Y.12/9/04EECS150 Lec26 - Summary9Transistor-level Logic Circuits - NAND•Inverter (NOT gate):•NAND gate•Logic Function: –out = 0 if f both a AND b = 1 ther efor e out = (ab)’–pFET netw ork and nF ET netw ork are duals of o ne ano ther.How about AND gate?a b out0 0 10 1 11 0 11 1 0nand (out, a, b)12/9/04EECS150 Lec26 - Summary10Combinational logic summary•Logic functions, truth tables, and switches–NOT, AND, OR, NAND, NOR, XOR, . . ., minimal set•Axioms and theorems of Boolean algebra–Proofs by re-writing and perfect induction•Gate logic–Networks of Boolean functions and their time behavior•Canonical forms–Two-level and incompletely specified functions•Optimization–Two-level simplification using K-maps–Automation of simplification–Multi-level logic•Later–Design case studies–Time behavior12/9/04EECS150 Lec26 - Summary11Transistor-level Logic Circuits - Latch•Positive Level-sensitive latch•Transistor Level•Positive Edge-triggered flip-flop built from two level-sensitive latches:clk’clkclkclk’D FlipFlop12/9/04EECS150 Lec26 - Summary1210 gatesD Flip-Flop•Make S and R complements of each other in Master stage–Eliminates 1s catching problem»Input only needs to settle by clock edge–Can't just hold previous value (must have new value ready every clock period)–Value of D just before clock goes low is what is stored in flip-flop–Can make R-S flip-flop by adding logic to make D = S + R' QDQQ'master stageslave stagePP'CLKRS QQ' RS QQ'12/9/04EECS150 Lec26 - Summary13Timing Methodologies•Rules for interconnecting components and clocks–Guarantee proper operation of system when strictly followed•Approach depends on building blocks used for memory elements–Focus on systems with edge-triggered flip-flops»Found in programmable logic devices–Many custom integrated circuits focus on level-sensitive latches•Basic rules for correct timing:–(1) Correct inputs, with respect to time, are provided to the flip-flops–(2) No flip-flop changes state more than once per clocking event12/9/04EECS150 Lec26 - Summary14there is a timing "window" around the clocking event during which the input must remain stable
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