Fall 2011 EECS150 Lecture 22Page 1EECS150 - Digital DesignLecture 22 – Power Consumption in CMOSNovember 22, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 22Page 2Announcements• Project check #5 out– Due end of next week– Final report due end of RRR week• Note on project grading– Individual check-offs treated like “homework”, graded on a curve– Most of credit will be assigned to final report– (I.e., plenty of opportunity to do well even if you are currently behind)– Have simplified the rest of the project to give everyone an excellent chance of completingFall 2011 EECS150 Lecture 22Page 3Announcements• Today is Elad’s last “official” lecture– Out of town next week; possible project review lecture during RRR• Next Tues. lecture will be given by John Lazzaro– Will discuss many practical examples of course material– E.g., iPad and MacBook Air - i.e., this will be a fun lecture!– Physical attendance required – HKN forms at end of lecture• Dan’s office hours on Wed. cancelled• Wed. lab will only be held from 11am – 2pm–Enjoy the holiday!Fall 2011 EECS150 Lecture 22Page 4Where Does Power Go In CMOS?•Two main components (focus for today):– Dynamic (switching) power: • Charging/discharging capacitors– Leakage power:• Transistors aren’t perfect switches• Additional components:– Crowbar (short-circuit):• Associated with transitions– Static• Biasing currents – should be zero in static CMOS logicFall 2011 EECS150 Lecture 22Page 5Side Note: Power vs. Energy• Power can (in principle) be made arbitrarily low…–How?• Energy per operation is often a more useful metric–E/op = Paverage* Taverage–No “cheating”Fall 2011 EECS150 Lecture 22Page 6Dynamic Power/EnergyFall 2011 EECS150 Lecture 22Page 7Dynamic Power/Energy• Power = Energy/transition · (Transition rate/2)= Energy/transition · (Rising transition rate)= CloadVdd2·f0Æ1= CloadVdd2·fclk· α0Æ1• α0Æ1is called “activity factor” Æ average probability of 0 to 1 transition– Will sometimes see P = (CloadVdd2 ·f · α), where α = 2α0Æ1• Power dissipation is data and logic dependentFall 2011 EECS150 Lecture 22Page 8Example Activity Factor Calculations (1)• Assume all primary inputs are equally likely to be 0 or 1– Not necessarily true in practice, but easy to handle a differentassumption• Activity factor of an inverter:Fall 2011 EECS150 Lecture 22Page 9Example Activity Factor Calculations (2)• Activity factor of a NAND gate:Fall 2011 EECS150 Lecture 22Page 10Notes on Activity Factor• Watch out for correlations between signals in complex circuits– Need to look at activity factor for whole circuit together, not just one gate at a time– (Verilog simulation is good for this)•Watch out for glitches Æ extra power…• What is the highest activity factor signal you are likely to have?Fall 2011 EECS150 Lecture 22Page 11Leakage Power• Transistors that are supposed to be off actually leak:Input at VDDInput at 0VDD0VVDDILeakVDD0VVDDILeakFall 2011 EECS150 Lecture 22Page 12Sub-Threshold Conduction• Drain current doesn’t immediately drop to 0 at VT:• Leakage drops exponentially as increase VT0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTExponentialFall 2011 EECS150 Lecture 22Page 13Leakage and Total Power• Assume that know average Ileak– (Note that Ileakis actually also state dependent – NMOS vs. PMOS leakage not identical)•Pleak= Ileak·Vdd•Ptotal= Pdyn+ PleakPtotal= α0Æ1CloadVdd2fclk+ IleakVddFall 2011 EECS150 Lecture 22Page 14Key Implications• Once you’ve done a “good” job with the design – I.e., gotten rid of all of the capacitance that doesn’t need to switch, used only the hardware you really needed, etc.• Biggest knob for reducing power is reducing Vdd– E/op proportional to Vdd2•But, reducing Vddreduces performance unless reduce VT–And reducing VTincreases Ileakexponentially– How to find the best balance?Fall 2011 EECS150 Lecture 22Page 15Energy-Performance Space• Plot all designs on a 2-D plane– No matter what you do, can’t get below/to the right of solid line• This line is called the “Pareto Optimal Curve”– Usually (always) follows law of diminishing returnsPerformanceEnergy/opFall 2011 EECS150 Lecture 22Page 16Optimization Perspective• Instead of looking at an “arbitrary” metric like “Energy*Delay”, this curve can answer questions like:– What is minimum energy for X performance?– Over what range of performance is a particular technique (dottedline) actually better?PerformanceEnergy/opFall 2011 EECS150 Lecture 22Page 17Key Observation• For optimal designs, “sensitivity” to all free parameters should be equal– Must equal slope of the Pareto curve – otherwise could trade one parameter for the otherPerformanceEnergy/opTTVTEnergy VSPerf V∂∂=∂∂DDDDVDDEnergy VSPerf V∂∂=∂∂Fall 2011 EECS150 Lecture 22Page 18Implications: Optimal Vddand VT• No single pair of optimal Vdd, VT– Depends on performance, power target– High performance: high Vdd, low VT– Low power: low Vdd, high VT• However, optimal Pleak/Pdynis roughly constant– Typically, Pleak ~ 30 – 50% of PdynFall 2011 EECS150 Lecture 22Page 19PipeliningPerformanceEnergy/opFall 2011 EECS150 Lecture 22Page
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