Spring 2009EECS150 - Lec11-proj1Page EECS150 - Digital DesignLecture 11 - Project Description, Part 1 of ?Feb 24, 2009John Wawrzynek1Spring 2009EECS150 - Lec11-proj1Page Project OverviewA. MIPS150 pipeline structureB. Memories, project memories and FPGAsC. Video subsystemD. Project specification and grading standard2Spring 2009EECS150 - Lec11-proj1Page MIPS 5-stage Pipeline Review3(IF)Use PC register as address to instruction memory (IMEM) and retrieve next instruction.(ID)Generate control signals, retrieve register values from regfile.(EX)Use ALU to compute result, memory address, or compare registers.(DM)Read or write data memory (DMEM).(WB)Send result back to regfile.Control Hazard ExampleSpring 2009EECS150 - Lec11-proj1Page MIPS 5-stage Pipeline4 beq $1, $2, L1IFIDEXDMWB add $5, $3, $4IFIDEXDMWBL1: sub $5, $3, $4IFIDEXDMWBbranch address ready herebut needed here!Register values are known here, move branch compare and target address generation to here.Still one remaining cycle of branch delay. “Architected branch delay slot” on MIPS allows compiler to deal with the delay. Other processors without architected branch-delay slot use branch predictors or pipeline stalling.cycleSpring 2009EECS150 - Lec11-proj1Page MIPS 5-stage Pipeline5 add $5, $3, $4IFIDEXDMWB add $7, $6, $5IFIDEXDMWBReg 5 value updated herereg 5 value needed here!Data Hazard ExampleNew value is actually known here. Send it directly from the output register of the the ALU to its input (and also down the pipeline to the register file).Logic must be added to detect when such a hazard exists and control multiplexors to forward correct value to ALU. No alternative except to stall pipeline (thus hurting performance).Spring 2009EECS150 - Lec11-proj1Page MIPS 5-stage Pipeline6 lw $5, offset($4)IFIDEXDMWBIFIDEXDMWBIFIDEXDMWBMemory value known herevalue needed here!Load Hazard Example“Architected load delay slot” on MIPS allows compiler to deal with the delay. Note, regfile still needs to be bypassed. No other alternative except for stalling. add $7, $6, $5 add $10, $9, $8 add $7, $6, $5 add $10, $9, $8Spring 2009EECS150 - Lec11-proj1Page Processor Pipelining7IF1IF2IDX1X2M1M2WBIF1IF2IDX1X2M1M2WBDeeper pipelines => less logic per stage => high clock rate.Deeper pipeline example.Deeper pipelines => more hazards => more cost and/or higher CPI.Remember, Performance = # instructions X Frequencyclk / CPIButCycles per instruction might go up because of unresolvable hazards.How about shorter pipelines ... Less cost, less performanceSpring 2009EECS150 - Lec11-proj1Page MIPS150 Pipeline8IXMThe blocks in the datapath with the greatest delay are: IMEM, ALU, and DMEM. Allocate one pipeline stage to each:Use PC register as address to IMEM and retrieve next instruction. Instruction gets stored in a pipeline register, also called “instruction register”, in this case.Most details you will need to work out for yourself. Some details to follow ... In particular, let’s look at hazards.Access data memory or I/O device for load or store. Allow for setup time for register file write.Use ALU to compute result, memory address, or compare registers for branch.Control Hazard ExampleSpring 2009EECS150 - Lec11-proj1Page MIPS 3-stage Pipeline9 beq $1, $2, L1IXM add $5, $3, $4IMXL1: sub $5, $3, $4IMbranch address ready herebut needed here!Architected branch delay slot allows us to delay branch target capture to here.Therefore no extra logic is required for stalling or other measures.Spring 2009EECS150 - Lec11-proj1Page MIPS 3-stage Pipeline10 lw $5, offset($4)IXMIXMIXMMemory value known here. It is written into the regfile on this edge.value needed here!Load Hazard add $7, $6, $5 add $9, $7, $8“Architected load delay slot” on MIPS allows compiler to deal with the delay. No regfile bypassing needed here. add $7, $6, $5 add $9, $7, $8Spring 2009EECS150 - Lec11-proj1Page MIPS 3-stage Pipeline11 add $5, $3, $4IXM add $7, $6, $5IXMreg 5 value updated herereg 5 value needed here!Data Hazard1. Stall the pipeline behind first add to wait for result to appear in register file. NOT ALLOWED this semester.2. Find a way to bypass the the M stage when not needed.a) Selectively forward ALU result back to input of ALU.b) Write result from X stage to register file without waiting for M stage.Ways to fix:Spring 2009EECS150 - Lec11-proj1Page 3-Stage Pipeline Data Hazard 12IXM add $7, $6, $5IXM add $9, $7, $8IXMSelectively forward ALU result back to input of ALU.• Traditional forwarding. Need to add mux at input to ALU, add control logic to sense when to activate. A bit complex to design. Check book for details.Write result from X stage to register file without waiting for M stage.reg 7 value written hereand read here. lw $5, offset($4)lw writes $5 here!When a lw instruction precedes a r-type instruction a “structural hazard” exists for the regfile write port. Both instructions need to write to reg file on same cycle. Solution: Add 2nd write port to regfile.Spring 2009EECS150 - Lec11-proj1Page Memory-Block Basics• Uses:Whenever a large collection of state elements is required. – data & program storage – general purpose registers – data buffering – table lookups – CL implementation • Basic Types:– RAM - random access memory – ROM - read only memory – EPROM, FLASH - electrically programmable read only memory 13Spring 2009EECS150 - Lec11-proj1Page Definitions Memory Interfaces for writing data: •Asynchronous (unclocked): A change in the address results in data appearing •Synchronous (clocked): A change in address, followed by an edge on CLK results in data appearing •Volatile: Looses its state when the power goes off. • Nonvolatile:Retains it state when power goes off.14Spring 2009EECS150 - Lec11-proj1Page Memory Components Types:• Volatile:– Random Access Memory (RAM): • DRAM "dynamic" • SRAM "static" • Non-volatile:– Read Only Memory (ROM): • Mask ROM "mask programmable" • EPROM "electrically programmable" • EEPROM "erasable electrically programmable" • FLASH memory - similar to EEPROM with programmer integrated on chip15Focus TodayAll these types are available as stand alone chips or as blocks in other chips.Spring 2009EECS150 - Lec11-proj1Page Standard Internal Memory Organization • RAM/ROM naming convention: – examples: 32 X 8, "32 by 8" => 32 8-bit
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