DOC PREVIEW
Berkeley COMPSCI 150 - Lecture 19

This preview shows page 1-2-3-4-5 out of 14 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

CS150 ProjectTips and AdviceDan Yeager, Daiwei Li, James ParkerTesting, testing, testingUnit testing● Requires you to modularize your design● Example modules:○ Branch decoder○ Memory mapping read/write○ Mem mask in/out○ Hazard unit○ Control/Datapath splitTesting, testing, testingUnit testing● Write tests before writing modules - test-driven development● See CacheTestBench.v, CacheTestTasks.vh, ALUTestBench.v for examples● Use tasks as "functions"● $random to generate random numbersTesting, testing, testingIntegration testing● Difficult to write a testbench for the entire CPU, too many signals!● Verify instruction-to-instruction behavior● Write software (assembly files)Testing, testing, testingWriting assembly tests:● ld file: (reference: http://www.math.utah.edu/docs/info/ld_3.html)SECTIONS{ . = 0x10000000; .text : { * (.start); * (.text); }}Testing, testing, testingWriting assembly tests:● Makefile:TARGET := <ld file>include ../Makefile.llvm.inTesting, testing, testingWriting assembly tests:● Assembly code:_start:li $s0, 0x00000020addi $t0, $t0, 20bne $t0, $s0, EndEnd:Avoiding bugs ● Issues with understanding?○ How does the UART work?○ What does it mean for memories to be synchronous?● Design document messy○ Do the design before writing the Verilog!● Bugs translating from design to code○ Don't code when tired○ Testbenches will help catch these bugsFixing bugs● Use make report - check for warnings/errors● Check for default values in case or if/else if statements● Check reset values● Check wire widths - these errors should be caught in synthesis● Use Modelsim○ Navigate to part of signal you care about○ e.g. EchoTestbench -> go to DataOutValid = 1StyleVerilog header file (.vh)● Constants: Opcode.vh`ifndef OPCODE`define OPCODE // Opcode`define RTYPE 6'b000000// Load/store`define LB 6'b100000`define LH 6'b100001`define LW 6'b100011`define LBU 6'b100100`define LHU 6'b100101...`endif //OPCODEStyleVerilog header file (.vh)● Tasks task SingleCacheWrite; input isDcache; input [31:0] task_addr; input [31:0] task_cache_din; input [3:0] task_cache_we; input task_expect_hit; begin SetupWrite(isDcache, task_addr, task_cache_din, task_cache_we); ClockInRequest(); WaitForStall(); VerifyWrite(isDcache, task_expect_hit); end endtaskStyle● Specify wire widths: 0 vs 32'b0○ Better yet, use a define for hardwired values● Multiple signal assignments○ For something complicated like control, should have spreadsheet■ Even better, generate Verilog from spreadsheet!○ {Signal1, Signal2, etc...} = {Signal1Val, Signal2Val, etc...};■ e.g. assign {opcode, rs, rt, rd, etc... } = {instruction[31:26], instruction[25:21], instruction[20:16], etc...}Style● always@(*) + case/if else instead of mux module instantiations and ? : statements○ Makes sense when you have a lot of muxes driven by the same signal○ Why? Easier to readStyle● Group "like" signals○ e.g. Put all pipeline registers in one always@(posedge clk) block● Label signals○ I_{}, X_{}, M_{} for signals from different


View Full Document

Berkeley COMPSCI 150 - Lecture 19

Documents in this Course
Lab 2

Lab 2

9 pages

Debugging

Debugging

28 pages

Lab 1

Lab 1

15 pages

Memory

Memory

13 pages

Lecture 7

Lecture 7

11 pages

SPDIF

SPDIF

18 pages

Memory

Memory

27 pages

Exam III

Exam III

15 pages

Quiz

Quiz

6 pages

Problem

Problem

3 pages

Memory

Memory

26 pages

Lab 1

Lab 1

9 pages

Memory

Memory

5 pages

Load more
Download Lecture 19
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 19 and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 19 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?