2/13/03 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Original Lab By: J. Wawrzynek and L.T. Pang Spring 2003 Changes by S. Pintz (2003) Lab 4 Verilog Design and Synthesis Objective You will design, debug, and implement a Finite State Machine (FSM). The FSM for this exercise is the combination lock example presented in class. Using our definition of the problem and our state transition diagram, you will derive a behavioral Verilog description of the state machine, enter your design in the HDL editor, simulate your design, synthesize the circuit, map it to the Xilinx FPGA, simulate the netlist, and finally download the design onto the Xilinx board and test it there. Introduction You are building the controller for a 2-bit serial lock used to control entry to a locked room. The lock has a RESET button, an ENTER button, and two two-position switches, CODE1 and CODE0, for entering the combination. For example, if the combination is 01-11, someone opening the lock would first set the two switches to 01 (CODE1 = low, CODE0 = high) and press ENTER. Then s/he would set the two switches to 11 (CODE1 = high, CODE0 = high) and press ENTER. This would cause the circuit to assert the OPEN signal, causing an electromechanical relay to be released and allowing the door to open. Our lock is insecure with only sixteen different combinations; think about how it might be extended. If the person trying to open the lock makes a mistake entering the switch combination, s/he can restart the process by pressing RESET. If s/he enters a wrong sequence, the circuitry would assert the ERROR signal, illuminating an error light. S/he must press RESET to start the process over. In this lab, you will enter a design for the lock’s controller in a new Xilinx project. Name this lab “lab4”. Make RESET and ENTER inputs. Use a two-bit wide input bus called CODE[1:0] for the two switches. (Information on how to use buses will be given later in this handout). The outputs are an OPEN signal and an ERROR signal. The table below summarizes the combination lock inputs and outputs: Input Signal Description RESET Clear any entered numbers ENTER Read the switches (enter a number in the combination) CODE[1:0] Two binary switches Output signal Description OPEN Lock opens ERROR Incorrect combination The following is a state transition diagram for this design:2/13/03 Figure 1: Combination Lock State Transition Diagram Detailed Specification Combination Comparator. You will need to design and implement a compare block based on the lock combination. This block processes the CODE[1:0] input signals into a simpler form for the FSM number, namely COM1 (COMpare 1) and COM2 (COMpare 2). Specifically, COM1 is asserted when CODE[1:0] is the combination’s first number and COM2 is asserted for the second number. Partitioning the circuit in this way makes the combination easy to change. 2 dipswitches on the board correspond to CODE[1:0]. Choose your own combination and fix them in your Verilog module; the two numbers must be different. This should be a simple block. Use a few AND gates and inverters, but write them in Verilog. Call this module compare.v Finite State Machine Module. The FSM module takes RESET, ENTER, COM1, COM2, and present state and generates OPEN and ERROR, as well as the next state. Figure 1 shows the state transition diagram. Note that unlike the diagram presented in the lecture notes, this diagram does not contain any arc corresponding to the RESET input. The FPGA flip-flops have a primitive reset option and therefore it is more efficient to let reset be part of the flip-flop specification rather than the next state logic. Also note that every output is assigned for every state. Make certain that your Verilog specification does the same. Call this module lock.v Remember to separate your FSM into 3 ALWAYS blocks as mentioned in the lab lecture. Debouncer and Edge detector for the ENTER signal. For correct operation of the FSM, the input signal ENTER, as it comes from the button press must be converted to a pulse that lasts for only one clock cycle. If your clock frequency is 16MHZ and you press the ENTER button for 1ms, then your system would interpret the ENTER signal has been asserted for thousands of cycles. In our case, since you are not changing the 2-bit input, your design might think you have entered the same combination thousands of times. For your debouncer, if its input has been asserted for 2 clock cycles (this makes sure the input signal is not some random glitch), then it will generate a pulse on the next clock cycle. This means the signal will asserted on the positive edge of the 3rd cycle and set low on the positive edge of the 4th cycle. The output of your debouncer will be used to drive the rest of your lock as the ENTER signal. START[ERROR=0OPEN=0]OK1[ERROR=0OPEN=0]BAD1[ERROR=0OPEN=0]OK2[ERROR=0OPEN=1]BAD2[ERROR=1OPEN=0]ENTER'ENTER'ENTER'ENTER & COM1ENTER & COM1'ENTER & COM2'ENTER & COM2ENTER2/13/03 Draw the signal observed at the output given an input pulse of arbitrary length longer than 3 clock periods. In the same way, the reset signal has to go through debouncing and edge detection circuits. However, the flip-flops used must not be reset by the reset signal. Can you explain why? Include your code for both debouncer circuits in locktop.v. Tasks Implement your design for the FSM in a Verilog behavioral model. Please use the sample Verilog FSM codes linked on the EECS150 website as references. You are to design two FSMs using different state assignment formats. For the first design, you must encode your states in 3 bits, but you can make up your own binary encoding. For the second design, you must use one-hot-encoding for your state assignment. Make sure you instantiate each module in the locktop.v file. Create a testbench and test the functionality of your design using the locktop.v file. When your design is functionally correct, use the FPGA.v ( this is the IO module given to you) file and check that the instantiation of the module lock_top in this file is correct. You should take a look at locktop.v to see its input and output ports are correctly defined. Synthesize and implement the design using the FPGA.v file for implementation on the XILINX XCV2000 FG680 device. Here is the proper synthesis/implementation
View Full Document
Unlocking...