Spring 2002 EECS150 - Lec14-seq1 Page 1EECS150 - Digital DesignLecture 14 - Sequential Circuits I(State Elements)March 12, 2002John WawrzynekSpring 2002 EECS150 - Lec14-seq1 Page 2Sequential CircuitsCircuit with feedback.• Examples:FSMD-type latchHow about CL logic with feedbackbut without register?• Sequential circuits exhibit eithersynchronous or asynchronousbehavior:– Synchronous: “state” of thecircuit changes at regularintervals controlled by a clock.– Asynchronous: state changeswith changing inputs. No clockpresent or circuit doesn’t waitfor it.Spring 2002 EECS150 - Lec14-seq1 Page 3Cross-coupled NOR gates• If both R=0 & S=0, then cross-couped NORsequivalent to a stable latch:• What happens if R or S or both become = 1?RS NOR00 101 010 011 0remember,RSQQ'01000 110Spring 2002 EECS150 - Lec14-seq1 Page 4Asynchronous State Transition DiagramQQ'01QQ'10QQ'00?SR=00 SR=00SR=10SR=01SR=11SR=01SR=11SR=10SR=00SR=10SR=01SR Latch:SR Q00 hold01 010 111 indeterminateSpring 2002 EECS150 - Lec14-seq1 Page 5Nand-gate based SR latchSpring 2002 EECS150 - Lec14-seq1 Page 6Level-sensitive SR Latch• The input “C” works as an “enable” signal, latch only changes outputwhen C is high.• usually connected to clock.• Generally, it is not a good idea to use a clock as a logic signal (intogates etc.). This is a special case.Spring 2002 EECS150 - Lec14-seq1 Page 7D-latchCompare to transistor version:Spring 2002 EECS150 - Lec14-seq1 Page 8Flip-flopsSpring 2002 EECS150 - Lec14-seq1 Page 9J-K FFJ K Q(t) Q(t+∆)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0holdresetsettoggle• Add logic to eliminate“indeterminate” action ofRS FF.• New action is “toggle”• J = “jam”• K = “kill”Spring 2002 EECS150 - Lec14-seq1 Page 10J-K Flip-flop from D-FFSpring 2002 EECS150 - Lec14-seq1 Page 11Toggle Flip-flop from D-FFSpring 2002 EECS150 - Lec14-seq1 Page 12Storage Element Taxonomy synchronous asynchronous level-sensitive edge-triggeredD-type é ü n.a.JK-type n.a. é n.a.RS-type ü ü é “latch” “flip-flop” “latch”Spring 2002 EECS150 - Lec14-seq1 Page 13Design Example with RS FF• With D-type FF state elements, new state iscomputedbased on inputs & present state bits - reloaded each cycle.• With RS (or JK) FF state elements, inputs are used todetermine conditions under which to set or reset state bits.• Example: bit-serial adder (LSB first)n-bit shift registern-bit shift registersscresetRFAFFBAWith D-FF for carrySpring 2002 EECS150 - Lec14-seq1 Page 14Bit-serial adder with RS FF• RS FF stores the carry:SRQab0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b ci ci+1 sCarry kill a’b’Carry generateabSpring 2002 EECS150 - Lec14-seq1 Page 15Resets/presetsSpring 2002 EECS150 - Lec14-seq1 Page 16Adding Reset/Presets• D-type flip-flop from latches:• Asynchronous reset in Flip-flop:Either inverter (or both) can be replaced by either NOR gate or NAND gate inthe second latch of the flip-flop. The second input to the gate is connectedto reset or preset signal. The choice of NOR versus NAND defines thesense of the reset/preset (active-high versus active-low). The choice whichinverter to replace defines reset versus preset.• Synchronous reset:A similar procedure as above is applied to the first latch of the flip-flop.Additional logic is needed to synchronize the reset signal with the correctlevel of the clock.D-latch
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