Fall 2002 EECS150 - Lec27-asynchPage 1EECS150 - Digital DesignLecture 27 - Asynchronous Sequential CircuitsNov 26, 2002John WawrzynekFall 2002 EECS150 - Lec27-asynchPage 2Outline• SR Latches and other storage elements• SynchronizersFigures from “Digital Design”, John F. WakerlyPrentice Hall, 2000An excellent treatment of the topic.• Purely asynchronous circuits– “self-timed” circuits– Mano has another class of asynchronous circuitsFall 2002 EECS150 - Lec27-asynchPage 3Cross-coupled NOR gates• If both R=0 & S=0, then cross-couped NORsequivalent to a stable latch:• If either R or S becomes =1 then state may change:• What happens if R or S or both become = 1?RS NOR00 101 010 011 0remember,RSQQ'01000110Fall 2002 EECS150 - Lec27-asynchPage 4Asynchronous State Transition DiagramQQ'01QQ'10QQ'00?SR=00 SR=00SR=10SR=01SR=11SR=01SR=11SR=10SR=00SR=10SR=01SR Latch:SR Q00 hold01 010 111 indeterminate• S is “set” input• R is “reset” inputFall 2002 EECS150 - Lec27-asynchPage 5Nand-gate based SR latch• Same behavior as cross-coupled NORs with invertered inputs.Fall 2002 EECS150 - Lec27-asynchPage 6Level-sensitive SR Latch• The input “C” works as an “enable” signal, latch only changes output when C is high.• usually connected to clock.Fall 2002 EECS150 - Lec27-asynchPage 7J-K FFJ K Q(t) Q(t+∆)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0holdresetsettoggle• Add logic to eliminate “indeterminate” action of RS FF.• New action is “toggle”•J = “jam”• K = “kill”JKQclkFall 2002 EECS150 - Lec27-asynchPage 8Storage Element Taxonomysynchronous asynchronouslevel-sensitive edge-triggeredD-type Ë 9 n.a.JK-type n.a. 9 n.a.RS-type 99 Ë“latch” “flip-flop” “latch”Ë“natural” form9 “possible” formFall 2002 EECS150 - Lec27-asynchPage 9Asynchronous Inputs to Synchronous Systems• Many synchronous systems need to interface to asynchronous input signals:– Consider a computer system running at some clock frequency, say 500MHz with:• Interrupts from I/O devices, keystrokes, etc.• Data transfers from devices with their own clocks– ethernet has its own 100MHz clock– PCI bus transfers, 66MHz standard clock.– These signals could have no known timing relationship with the system clock of the CPU.Fall 2002 EECS150 - Lec27-asynchPage 10“Synchronizer” Circuit• For a single asynchronous input, we use a simple flip-flop to bring the external input signal into the timing domain of the system clock:• The D flip-flop samples the asynchronous input at each cycle and produces a synchronous output that meets the setup time of the next stage.Fall 2002 EECS150 - Lec27-asynchPage 11“Synchronizer” Circuit• It is essential for asynchronous inputs to be synchronized at only one place. • Two flip-flops may not receive the clock and input signals at precisely the same time (clock and data skew). • When the asynchronous changes near the clock edge, one flip-flop may sample input as 1 and the other as 0.Fall 2002 EECS150 - Lec27-asynchPage 12“Synchronizer” Circuit• Single point of synchronization is even more important when input goes to a combinational logic block (ex. FSM)• The CL block can accidentally hide the fact that the signal is synchronized at multiple points.• The CL magnifies the chance of the multiple points of synchronization seeing different values.• Sounds simple, right?Fall 2002 EECS150 - Lec27-asynchPage 13Synchronizer Failure & Metastability• We think of flip-flops having only two stable states - but all have a third metastable state halfway between 0 and 1.• When the setup and hold times of a flip-flop are not met, the flip-flop could be put into the metastable state. • Noise will be amplified and push the flip-flop one way or other.• However, in theory, the time to transition to a legal state is unbounded.• Does this really happen?• The probability is low, butthe number of trials is high!Fall 2002 EECS150 - Lec27-asynchPage 14Synchronizer Failure & Metastability• If the system uses a synchronizer output while the output is still in the metastable state ⇒ synchronizer failure.• Initial versions of several commercial ICs have suffered from metastability problems - effectively synchronization failure:– AMD9513 system timing controller– AMD9519 interrupt controller– Zilog Z-80 Serial I/O interface– Intel 8048 microprocessor– AMD 29000 microprocessor• To avoid synchronizer failure wait long enough before using a synchronizer’s output. “Long enough”, according to Wakerly, is so that the mean time between synchronizer failures is several orders ofmagnitude longer than the designer’s expected length of employment!• In practice all we can do is reduce the probability of failure to a vanishing small value.Fall 2002 EECS150 - Lec27-asynchPage 15Reliable Synchronizer Design• The probability that a flip-flop stays in the metastable state decreases exponentially with time. • Therefore, any scheme that delays using the signal can be used to decrease the probability of failure. • In practice, delaying the signal by a cycle is usually sufficient:• If the clock period is greater than metastability resolution time plus FF2 setup time, FF2 gets a synchronized version of ASYNCIN.• Multi-cycle synchronizers (using counters or more cascaded flip-flops) are even better.Fall 2002 EECS150 - Lec27-asynchPage 16Purely Asynchronous Circuits• Many researchers (and a few industrial designers) have proposed a variety of circuit design methodologies that eliminate the need for a globally distributed clock. • They cite a variety of important potential advantages over synchronous systems (will list later).• To date, these attempts have remained mainly in Universities.• A few commercial asynchronous chips/systems have been build.• Sometimes, asynchronous blocks sometimes appear inside otherwisesynchronous systems.• Asynchronous techniques have long been employed in DRAM and other memory chips for generation internal control without external clocks. (Precharge/sense-amplifier timing based on address line changes.)• These techniques are generally interesting, and if nothing else help put synchronous design in perspective.Fall 2002 EECS150 - Lec27-asynchPage 17Synchronous Data Transfer• In synchronous systems, the clock signal is used to coordinate
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