CS 150 – Fall 2007 - Lec #27: FPGA Evolution – 1trend toward higher levels of integrationEvolution of Implementation Technologies! Discrete devices: relays, transistors (1940s-50s)! Discrete logic gates (1950s-60s)! Integrated circuits (1960s-70s)" e.g. TTL packages: Data Book for 100’s of different parts" Map your circuit to the Data Book parts! Gate Arrays (IBM 1970s)" “Custom” integrated circuit chips" Design using a library (like TTL)" Transistors are already on the chip" Place and route software puts the chip together automatically" + Large circuits on a chip" + Automatic design tools (no tedious custom layout)" - Only good if you want 1000’s of partsCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 2Gate Array Technology (IBM - 1970s)! Simple logic gates" Use transistors toimplement combinationaland sequential logic! Interconnect" Wires to connect inputs andoutputs to logic blocks! I/O blocks" Special blocks at peripheryfor external connections! Add wires to make connections" Done when chip is fabed# “mask-programmable”" Construct any circuitCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 3Programmable Logic! Disadvantages of the Data Book method" Constrained to parts in the Data Book" Parts are necessarily small and standard" Need to stock many different parts! Programmable logic" Use a single chip (or a small number of chips)" Program it for the circuit you want" No reason for the circuit to be smallCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 4Programmable Logic Technologies! Fuse and anti-fuse" Fuse makes or breaks link between two wires" Typical connections are 50-300 ohm" One-time programmable (testing before programming?)" Very high density! EPROM and EEPROM" High power consumption" Typical connections are 2K-4K ohm" Fairly high density! RAM-based" Memory bit controls a switch that connects/disconnects two wires" Typical connections are .5K-1K ohm" Can be programmed and re-programmed in the circuit" Low densityCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 5Programmable Logic! Program a connection" Connect two wires" Set a bit to 0 or 1! Regular structures for two-level logic (1960s-70s)" All rely on two-level logic minimization" PROM connections - permanent" EPROM connections - erase with UV light" EEPROM connections - erase electrically" PROMs# Program connections in the _____________ plane" PLAs# Program the connections in the ____________ plane" PALs# Program the connections in the ____________ planeCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 6PAL Logic Building Block! Programmable AND gates! Fixed OR/NOR gate! Flipflop/Registered Output! Feedback to Array! Tri-state OutputCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 7XOR PALs! Useful for comparator logic, arithmetic sums, etc." Use of XOR gates can dramatically reduce the number ofAND plane inputs needed to realize certain functionsCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 8XOR PAL! And/Or/XOR Logic! Feedback! Registered Outputs! Tri-State OutputsCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 9Another Variation: Synchronous vs.Asynchronous OutputsDQDQDQQ0Q1OpenComSeqSeqCLKNDResetCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 10Making Large Programmable Logic Circuits! Alternative 1 : “CPLD”" Put a lot of PLDS on a chip" Add wires between them whose connections can beprogrammed" Use fuse/EEPROM technology! Alternative 2: “FPGA”" Emulate gate array technology" Hence Field Programmable Gate Array" You need:# A way to implement logic gates# A way to connect them togetherCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 11Field-Programmable Gate Arrays! PALs, PLAs = 10s – 100s Gate Equivalents! Field Programmable Gate Arrays = FPGAs" Altera MAX Family" Actel Programmable Gate Array" Xilinx Logical Cell Array! 1000s - 100000(s) of Gate Equivalents!CS 150 – Fall 2007 - Lec #27: FPGA Evolution – 12Field-Programmable Gate Arrays! Logic blocks" To implement combinationaland sequential logic! Interconnect" Wires to connect inputs andoutputs to logic blocks! I/O blocks" Special logic blocks atperiphery of device forexternal connections! Key questions:" How to make logic blocks programmable?" How to connect the wires?"After the chip has been fab’dCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 13Tradeoffs in FPGAs! Logic block - how are functions implemented: fixed functions(manipulate inputs) or programmable?" Support complex functions, need fewer blocks, but they are biggerso less of them on chip" Support simple functions, need more blocks, but they are smaller somore of them on chip! Interconnect" How are logic blocks arranged?" How many wires will be needed between them?" Are wires evenly distributed across chip?" Programmability slows wires down –!are some wires specialized tolong distances?" How many inputs/outputs must be routed to/from each logic block?" What utilization are we willing to accept? 50%? 20%? 90%?CS 150 – Fall 2007 - Lec #27: FPGA Evolution – 14Clk MUXOutput MUXQF/B MUXInvert ControlAND ARRAYCLKpad8 Product TermAND-OR Array+ProgrammableMUX'sProgrammable polarityI/O PinSeq. LogicBlockProgrammable feedbackAltera EPLD (Erasable ProgrammableLogic Devices)! Historical Perspective" PALs: same technology as programmed once bipolar PROM" EPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light! Altera building block = MACROCELLCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 15Altera EPLDs contain 10s-100s of independently programmed macrocellsPersonalizedby EPROMbits:Flipflop controlledby global clock signallocal signal computesoutput enableFlipflop controlledby locally generatedclock signal+ Seq Logic: could be D, T positive or negative edge triggered+ product term to implement clear functionSynchronous ModeAsynchronous ModeGlobal CLKOE/Local CLKEPROM Cell1Global CLKOE/Local CLKEPROM Cell1Clk MUXClk MUXQQAltera EPLD: Synchronous vs.Asynchronous ModeCS 150 – Fall 2007 - Lec #27: FPGA Evolution – 16LAB A LAB HLAB B LAB GLAB CLAB FLAB DLAB EP I AAND-OR structures are relatively limited Cannot share signals/product terms among macrocellsLogicArrayBlocks(similar tomacrocells)Global Routing:ProgrammableInterconnectArray8 Fixed Inputs52 I/O Pins8 LABs16 Macrocells/LAB32 Expanders/LABEPM5128:Altera Multiple Array Matrix (MAX)CS 150 – Fall 2007 - Lec #27: FPGA Evolution – 17LAB ArchitectureExpander Terms shared among allmacrocells within the LAB• Efficient way to use AND plane resourcesMacrocell
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