Spring 2010EECS150 - Lec14-proj3Page EECS150 - Digital DesignLecture 14 - Project Description, Part 3March 4, 2010John Wawrzynek1Spring 2010EECS150 - Lec14-proj3Page Verilog Memory Synthesis Notes• Block RAMS and LUT RAMS all exist as primitive library elements (similar to FDRSE) and can be instantiated. However, it is much more convenient to use inference.• Depending on how you write your verilog, you will get either a collection of block RAMs, a collection of LUT RAMs, or a collection of flip-flops.• The synthesizer uses size, and read style (synch versus asynch) to determine the best primitive type to use. • It is possible to force mapping to a particular primitive by using synthesis directives. However, if you write your verilog correctly, you will not need to use directives.• The synthesizer has limited capabilities (eg., it can combine primitives for more depth and width, but is limited on porting options). Be careful, as you might not get what you want.• See Synplify User Guide, and XST User Guide for examples.2Spring 2010EECS150 - Lec14-proj3Page Inferring RAMs in Verilog3 // 64X1 RAM implementation using distributed RAM module ram64X1 (clk, we, d, addr, q);input clk, we, d;input [5:0] addr;output q; reg [63:0] temp; always @ (posedge clk)if(we) temp[addr] <= d; assign q = temp[addr]; endmoduleAsynchronous read infers LUT RAMVerilog reg array used with “always @ (posedge ... infers memory array.Spring 2010EECS150 - Lec14-proj3Page Dual-read-port LUT RAM4// // Multiple-Port RAM Descriptions // module v_rams_17 (clk, we, wa, ra1, ra2, di, do1, do2); input clk; input we; input [5:0] wa; input [5:0] ra1; input [5:0] ra2; input [15:0] di; output [15:0] do1; output [15:0] do2; reg [15:0] ram [63:0]; always @(posedge clk) begin if (we) ram[wa] <= di; end assign do1 = ram[ra1]; assign do2 = ram[ra2]; endmoduleMultiple reference to same array.Spring 2010EECS150 - Lec14-proj3Page Block RAM Inference5// // Single-Port RAM with Synchronous Read // module v_rams_07 (clk, we, a, di, do); input clk; input we; input [5:0] a; input [15:0] di; output [15:0] do; reg [15:0] ram [63:0]; reg [5:0] read_a; always @(posedge clk) begin if (we) ram[a] <= di; read_a <= a; end assign do = ram[read_a]; endmodule Synchronous read (registered read address) infers Block RAMSpring 2010EECS150 - Lec14-proj3Page Block RAM initialization6module RAMB4_S4 (data_out, ADDR, data_in, CLK, WE); output[3:0] data_out; input [2:0] ADDR; input [3:0] data_in; input CLK, WE; reg [3:0] mem [7:0]; reg [3:0] read_addr; initial begin $readmemb("data.dat", mem); end always@(posedge CLK) read_addr <= ADDR; assign data_out = mem[read_addr]; always @(posedge CLK) if (WE) mem[ADDR] = data_in; endmodule“data.dat” contains initial RAM contents, it gets put into the bitfile and loaded at configuration time. (Remake bits to change contents)Spring 2010EECS150 - Lec14-proj3Page Dual-Port Block RAM7module test (data0,data1,waddr0,waddr1,we0,we1,clk0, clk1, q0, q1); parameter d_width = 8; parameter addr_width = 8; parameter mem_depth = 256; input [d_width-1:0] data0, data1; input [addr_width-1:0] waddr0, waddr1; input we0, we1, clk0, clk1; reg [d_width-1:0] mem [mem_depth-1:0] reg [addr_width-1:0] reg_waddr0, reg_waddr1; output [d_width-1:0] q0, q1; assign q0 = mem[reg_waddr0]; assign q1 = mem[reg_waddr1]; always @(posedge clk0) begin if (we0) mem[waddr0] <= data0; reg_waddr0 <= waddr0; end always @(posedge clk1) begin if (we1) mem[waddr1] <= data1; reg_waddr1 <= waddr1; end endmoduleSpring 2010 EECS150 – Lec14-proj3Page First-in-first-out (FIFO) Memory• Used to implement queues. • These find common use in computers and communication circuits.• Generally, used to “decouple” actions of producer and consumer:• Producer can perform many writes without consumer performing any reads (or vis versa). However, because of finite buffer size, on average, need equal number of reads and writes.• Typical uses: – interfacing I/O devices. Example network interface. Data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized.– Example: Audio output. Processor produces output samples in bursts (during process swap-in time). Audio DAC clocks it out at constant sample rate.stating stateafter writeafter readabcabcdbcdSpring 2010 EECS150 – Lec14-proj3Page FIFO Interfaces• After write or read operation, FULL and EMPTY indicate status of buffer.• Used by external logic to control own reading from or writing to the buffer.• FIFO resets to EMPTY state.• HALF FULL (or other indicator of partial fullness) is optional.• Address pointers are used internally to keep next write position and next read position into a dual-port memory.•If pointers equal after write ⇒ FULL:•If pointers equal after read ⇒ EMPTY:DINDOUTWEREEMPTYFULLHALF FULLRST CLKFIFOwrite ptrread ptrwrite ptr read ptrwrite ptr read ptrSpring 2010 EECS150 – Lec14-proj3Page FIFO Implementation Details WE RE equal EMPTYi FULLi 0 0 0 0 0 0 0 1 EMPTYi-1 FULLi-1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 EMPTYi-1 FULLi-1 • Assume, dual-port memory with asynchronous read, synchronous write.• Binary counter for each of read and write address. CEs (count enable) controlled by WE and RE.• Equal comparator to see when pointers match.• Flip-flop each for FULL and EMPTY flags: • Control logic (FSM) with truth-table shown to left.Spring 2010 EECS150 – Lec14-proj3Page Xilinx Virtex5 FIFOs• Virtex5 BlockRAMS include dedicated circuits for FIFOs.• Details in User Guide (ug190).• Takes advantage of separate dual ports and independent ports clocks.Spring 2010EECS150 - Lec14-proj3Page Processor Design Considerations (1/2)• Register File: Consider distributed RAM (LUT RAM)– Size is close to what is needed: distributed RAM primitive
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