University of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS 150 Fall 2000Check Point 2UART Design1 ObjectiveIn this lab you will design, simulate, implement, an universal asynchronous receiver /transmitter circuit (UART).2 Functional SpecificationUARTs are used for communication between two devices. For instance, UARTs are usedto connect terminals to computers. They provide a means to send data with a minimum ofwires, in our case this is the shared bus. The data is sent bit-serially (one bit at a time),and no clock signal is sent along with it. The primary function of a UART is parallel-to-serial conversion when transmitting, and serial-to-parallel conversion when receiving.The fact that a clock is not transmitted with the data complicates the design of a UART.The two systems (sender and receiver) have separate, unsynchronized, clock signals.Although the two clocks will have roughly the same frequency, they will not have thesame phase. Part of a UART’s function, and the tricky part, is to “sample” the serialinput at just the right time to reliably capture the bit stream. This is done by using a high-speed clock to sample the bit stream multiple times per data bit.In our application the bit transfer rate, or baud rate, is 250kHz. Your FPGA board isequipped with a 16MHz crystal oscillator. A 250kHz clock signal could be generated bydividing the crystal oscillator frequency. We do not actually need that frequency for thislab. The frequency we need is 8 times the baud rate: 8 × (250kHz) = 2MHz.Figure 1 shows a functional block diagram of the UART receiver that you will design.Bit-serial data is received on the SERIAL-IN.H input. When one byte of data has beenreceived, it is output to the D output bus, and the output control signal DRDY.H isasserted for one clock period. The block is clocked with a frequency 8 times the baudrate, in this case 250kHz.UART / RXD[7:0]DRDY.HRESET.HSERIAL-IN.H (RX)ClockFigure 1: UART Receiver symbol.Data is transferred one byte at a time to the receiver using the format shown in Figure 3.The transmission character is composed of an 8-bit data byte, sent LSB first, preceded bya start bit (LOW) and followed by a stop bit (HIGH). When no character is beingtransmitted, the line is idle (HIGH). The line need not go idle between characters, as it ispossible for the start bit of a transmission to immediately follow the stop bit of theprevious transmission. We also need a TX enable line that enable the line-driver in thetransceiver chip when we are transmitting something.3 Theory of OperationThis section describes the internal operation of the UART receiver that you will design.There are many possible detailed designs – we will not present them all here, but we willgive you some ideas.StartIdle D0 D1 D2 D3 D4 D5 D6 D7 Stop IdleTimeFigure 3: A UART transmission.TXTX_EFigure 2: UART Transmitter symbol.UART / TXD[7:0]SEND.HRESET.HSERIAL-OUT.H (TX)ClockOUTPUT_ENABLE (TX_E)TransmittingThe transmitter is easier to implement so I will discuss it first. You will probablywant to use a loadable shift register to do the parallel to serial conversion. Also since youwill be receiving a 8x baud-rate clock you will need to make sure you do the parallel toserial conversion at the right speed (1x baud-rate). This can be achieved by dividing theincoming clock by 8 and using that slower clock for the shift register. Another approachis to generate a shift enable once every 8 cycles (I used this one although it is not clear tome if either method is better than the other). You will also need to generate a transmittingsignal to tell the FSM that you are busy and not to send anything else till you are done.This can be done by a counter to keep track of the bits that you have sent or if you areclever just logic on the content of the shift register (if you constructed the shift registerthe right way). Also when the transmitter is idle the output line should stay 1, and theTX_E line should be 0.The receiver is a bit more complicated since it is responsible for catchingtransmission on the asynchronous bus transmitted by another transmitter that probablyhas a clock with different phase (meaning the other clock does not have to have an edgeexactly the same time) and potentially even tiny bit different in period. To counter thesedifficulties we make the receiver super-sample the data input line. We will use 8x super-sample, this means that even though data is coming at a rate of 250Kbits/s we will belooking at the input 2M times/s.We will use the super super-sampling approach to find the exact begging of aUART transmission. We can do that by looking for a falling edge on the serial input line(yes I say edge but this has NOTHING to do with a clock input on anything, so don’teven think about feeding anything other than a clock into a clock input). An edge detectorlooks somewhat like debouncer. Once you find the falling edge of that first start bit thenyou offset your shift register’s sampling time so that it will sample at exactly the middleof data bits, right when each bit is “halfway” transmitted. See picture below.Again there are different ways of doing this one possible way will be covered in the Lablecture so pay attention to Jeff when he’s talking.Serialdata inputSample HereIn addition to sampling your receiver will also need to keep track of when the lineis idle, when it is receiving transmission and when it finished receiving a transmission,and if the transmission was valid (i.e. start bit = 0, stop bit = 1). This is accomplishedwith an FSM, and probably a counter to make sure you’ve shifted in the appropriate # ofbits. And since you are shifting data in you’d probably want to use a shift register.Yourreceiver will also need to provide a data present signal to tell the rest of your system thata transmission has been received and present the rest of the system with the byte of datathe it received.Pit fall:Your UART designs will be clocked at 2MHz as opposed to the rest of yoursystem (8 or 16MHz). This presents an interesting problem when you need it to talk tothe rest of the system. See if you can figure this one out yourself. This might not be a bigproblem for this checkpoint as you can just as well clock the rest of your system at 2MHzbut that will not be possible (or at least
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