Fall 2011 EECS150 Lecture 21Page 1EECS150 - Digital DesignLecture 21 – Arithmetic Blocks 2 and ShiftersNovember 15, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 21Page 2Announcements• Project checkpoint #4b due this Fri. • Project checkpoint #5 out this week–Due Fri. Dec. 1stFall 2011 EECS150 Lecture 21Page 3Adder ReviewFall 2011 EECS150 Lecture 21Page 4Binary Multiplication ExampleFall 2011 EECS150 Lecture 21Page 5Multiplication In Generala3a2a1a0Multiplicandb3b2b1b0Multipliera3b0a2b0a1b0a0b0a3b1a2b1a1b1a0b1Partiala3b2a2b2a1b2a0b2productsa3b3a2b3a1b3a0b3 . . . a1b0+a0b1a0b0ProductMany different circuits exist for multiplication.Each has a different balance between speed, power, and area.Fall 2011 EECS150 Lecture 21Page 6Side Note: Signed MultiplicationRememberfor 2’s complement numbers MSB has negative weightex: -6 = 110102= 0•20+ 1•21+ 0•22+ 1•23-1•24= 0 + 2 + 0 + 8 - 16 = -6• Therefore:a) subtract final partial productb) sign-extend partial productsFall 2011 EECS150 Lecture 21Page 7Sequential “Shift and Add” Multiplier•Sums each partial product, one at a time.• In binary, each partial product is a shifted version of A or 0.Control Algorithm:1. P ← 0, A ← multiplicand, B ← multiplier2. If LSB of B==1 then add A to Pelse add 03. Shift [P][B] right by 14. Repeat steps 2 and 3 n-1 times.5. [P][B] has product.•Cost α n, Τ = n clock cycles.• What is the critical path for determining the min clock period?Fall 2011 EECS150 Lecture 21Page 8Array MultiplierSingle cycle multiply: Generates all n partial products simultaneously.Y0Y1X3X2X1X0X3HAX2FAX1FAX0HAY2X3FAX2FAX1FAX0HAZ1Z3Z6Z7Z5Z4Y3X3FAX2FAX1FAX0HAZ2Z0Ex: Z[7:0] = X[3:0] * Y[3:0]Fall 2011 EECS150 Lecture 21Page 9Array Multiplier Critical PathHA FA FA HAHAFAFAFAFAFA FA HACritical Path 1Critical Path 2Critical Path 1 & 2()()()12 1mult carry sum andtMNtNtt⎡⎤≈−+−⋅+−⋅+⎣⎦Fall 2011 EECS150 Lecture 21Page 10Carry-Save Multiplier• Big difference: final add can use fast (tree/CLA) structure HA HA HA HAFAFAFAHAFAHA FA FAFAHA FA HAVector Merging Adder()1mult and carry mergett Ntt=+−⋅ +Fall 2011 EECS150 Lecture 21Page 11Carry-Save MultiplierAddition is associative and communitive. For example:(((X0 + X1)+X2 )+X3 ) = ((X0 + X1)+(X2 +X3 ))• A balanced tree can be used to reduce the logic delay.• Basis of Wallace Tree Multiplier.• (i.e., min. # of CSA levels to reach addition of two binary numbers)• Multiplier delay α log3/2N + log2NFall 2011 EECS150 Lecture 21Page 12Constant Multiplication•Our discussion so far has assumed both the multiplicand (A) and the multiplier (B) can vary at runtime.• What if one of the two is a constant? Ex:Y = C*Xwhere C is an application dependent constant that is hard-wired into the circuit.• (“Constant Coefficient” multiplication comes up often in e.g. signal processing)• How do we build an array multiplier that takes advantage of the constancy of one of the operands?Fall 2011 EECS150 Lecture 21Page 13Multiplication by a Constant• If the constant C in C*X is a power of 2, then the multiplication is simply a shift of X. •Ex: 4*X• What about multiplication by non- powers of 2?Fall 2011 EECS150 Lecture 21Page 14Multiplication by a Constant• In general, a combination of fixed shifts and addition:– Ex: 6*X = 0110 * X = (22+ 21)*X–Details:Fall 2011 EECS150 Lecture 21Page 15Multiplication by a Constant• Another example: C = 2310= 010111•In general, the number of additions equals the number of 1’s in the constant minus one.• Using carry-save adders (for all but one of these) helps reduce the delay and cost, but the number of adders is still set by thenumber of 1’s in C.• Is there a way to further reduce the number of adders (and thus the cost and delay)?Fall 2011 EECS150 Lecture 21Page 16Multiplication using Subtraction•Subtraction roughly the same cost and delay as addition.• Consider C*X where C is the constant value 1510= 01111.C*X requires 3 additions.• We can “recode” 15 from 01111 = (23+ 22 + 21 + 20 )to 10001 = (24-20 )where 1 means negative weight.• Therefore, 15*X can be implemented with only one subtractor.Fall 2011 EECS150 Lecture 21Page 17Canonic Signed Digit Representation• CSD represents numbers using 1, 1, & 0 with the least possible number of non-zero digits. – Strings of 2 or more non-zero digits are replaced.– Leads to a unique representation.• To form CSD representation might take 2 passes:– First pass: replace all occurrences of 2 or more 1’s: 01..10 by 10..10– Second pass: same as a above, plus replace 0110 by 0010•Examples:• Can we further simplify the multiplier circuits?0010111 = 2300110010101001 = 32 - 8 - 1011101 = 29100101 = 32 - 4 + 10110110 = 5410110101001010 = 64 - 8 - 2Fall 2011 EECS150 Lecture 21Page 18“Constant Coefficient Multiplication” (KCM)Fall 2011 EECS150 Lecture 21Page 19Fixed Shifters / RotatorsFall 2011 EECS150 Lecture 21Page 20Variable Shifters / Rotators• Sequential version:• How about doing it in one cycle?Fall 2011 EECS150 Lecture 21Page 21Log Shifter / Rotator• Log(N) stages, each shifts (or not) by a power of 2 places, S=[s2;s1;s0]:Fall 2011 EECS150 Lecture 21Page 22“Improved” Shifter / Rotator• How about this approach? Can it lead to even less delay?• Key questions: – What is the delay of the big muxes?– How does the “cost” scale? • Look at transistor-level implementationFall 2011 EECS150 Lecture 21Page 23Barrel Shifter•Cost/delay?– (don’t forget the decoder)Fall 2011 EECS150 Lecture 21Page 24Connection Matrix• Generally useful structure:–N2control points. – What other interesting functions can it do?Fall 2011 EECS150 Lecture 21Page 25Cross-bar Switch• Nlog(N) control signals.• Supports all interesting permutations– All one-to-one & one-to-many connections.• Commonly used in communication hardware (switches,
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