CS 150 - Spring 2007 – Lec. #3: Programmable Logic - 1Programmable Logic! Regular logic" Programmable Logic Arrays" Multiplexers/Decoders" ROMs! Field Programmable Gate Arrays" Xilinx Vertex“Random Logic”Full Custom Design“Regular Logic”Structured DesignCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 2• • •inputsANDarray• • •outputsORarrayproducttermsProgrammable Logic Arrays (PLAs)! Pre-fabricated building block of many AND/OR gates" Actually NOR or NAND" ”Personalized" by making or breaking connections among gates" Programmable array block diagram for sum of products formCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 3example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + Apersonality matrix1 = uncomplemented in term0 = complemented in term– = does not participate1 = term connected to output0 = no connection to outputinput side:output side:product inputs outputsterm A B C F0 F1 F2 F3AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1reuse of termsEnabling Concept! Shared product terms among outputsCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 4Before Programming! All possible connections available before "programming"" In reality, all AND and OR gates are NANDsCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 5AB CF1 F2 F3F0ABB'CAC'B'C'AAfter Programming! Unwanted connections are "blown"" Fuse (normally connected, break unwanted ones)" Anti-fuse (normally disconnected, make wanted connections)CS 150 - Spring 2007 – Lec. #3: Programmable Logic - 6notation for implementingF0 = A B + A' B'F1 = C D' + C' DAB+A'B'CD'+C'DABA'B'CD'C'DA B C DAlternate Representation for High Fan-inStructures! Short-hand notation--don't have to draw all the wires" Signifies a connection is present and perpendicular signal isan input to gateCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 7A B C F1 F2 F3 F4 F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1A'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABCA B CF1 F2 F3 F4 F5F6full decoder as for memory addressbits stored in memoryProgrammable Logic Array Example! Multiple functions of A, B, C" F1 = A B C" F2 = A + B + C" F3 = A' B' C'" F4 = A' + B' + C'" F5 = A xor B xor C" F6 = (A xnor B xnor C)’CS 150 - Spring 2007 – Lec. #3: Programmable Logic - 80 1 X 00 1 X 0 0 0 X X0 0 X X DABCminimized functions:W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –0 0 X 10 1 X 1 0 1 X X0 1 X X DABCK-map for W K-map for X0 1 X 00 1 X 0 1 1 X X1 1 X X DABCK-map for YPLA Design Example! BCD to Gray code converterK-map for Z0 0 X 11 0 X 0 0 1 X X1 0 X X DABCCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 9not a particularly goodcandidate for PLAimplementation since no terms are shared among outputshowever, much more compact and regular implementation when compared with discrete AND and OR gatesA B C DW X Y ZABDBCBC'BCA'B'C'DBCDAD'BCD'minimized functions:W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'PLA Design Example (cont’d)! Code converter: programmed PLACS 150 - Spring 2007 – Lec. #3: Programmable Logic - 100 1 X 00 1 X 0 0 0 X X0 0 X X DABCminimized functions:W =X = Y = Z = A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –0 0 X 10 1 X 1 0 1 X X0 1 X X DABCK-map for W K-map for X0 1 X 00 1 X 0 1 1 X X1 1 X X DABCK-map for YPLA Design Example! BCD to Gray code converterK-map for Z0 0 X 11 0 X 0 0 1 X X1 0 X X DABCCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 110 1 X 00 1 X 0 0 0 X X0 0 X X DABCminimized functions:W =X = Y = Z = A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –0 0 X 10 1 X 1 0 1 X X0 1 X X DABCK-map for W K-map for X0 1 X 00 1 X 0 1 1 X X1 1 X X DABCK-map for YPLA Design Example #1! BCD to Gray code converterK-map for Z0 0 X 11 0 X 0 0 1 X X1 0 X X DABCBC’CS 150 - Spring 2007 – Lec. #3: Programmable Logic - 12EQ NE LT GTA'B'C'D'A'BC'DABCDAB'CD'AC'A'CB'DBD'A'B'DB'CDABCBC'D'A B C DPLA Design Example #2! Magnitude comparator1 0 0 00 1 0 0 0 0 1 00 0 0 1 DABC0 1 1 11 0 1 1 1 1 0 11 1 1 0 DABC0 0 0 01 0 0 0 1 1 0 11 1 0 0 DABC0 1 1 10 0 1 1 0 0 0 00 0 1 0 DABCK-map for EQK-map for NEK-map for GTK-map for LTCS 150 - Spring 2007 – Lec. #3: Programmable Logic - 13multiplexer demultiplexer 4x4 switchcontrolcontrolMultiplexer/Demultiplexer: MakingConnections! Direct point-to-point connections between gates!Multiplexer: route one of many inputs to …
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