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Berkeley COMPSCI 150 - Lec 19 – Putting it together

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EECS 150 - Components and Design Techniques for Digital SystemsLec 19 – Putting it togetherCase Study: A Serial Line Transmitter/Receiver10-30-07David E. CullerElectrical Engineering and Computer SciencesUniversity of California, BerkeleyOutline• Quick Review• A Serial Line Transmitter/Receiver– Designing hardware to communicate over a single wire.– The data will be sent serially– The clocks on the two ends are completely asynchronous.– Communication protocol – RS232Recall: Levels of Design RepresentationTransfer FunctionTransistor PhysicsDevicesGatesCircuitsFlipFlopsEE 40HDLMachine OrganizationInstruction Set ArchPgm Language Asm / Machine LangCS 61CDatapath + Control• Datapath: Storage, FU, interconnect sufficient to perform the desired functions– Inputs are Control Points– Outputs are signals• Controller: State machine to orchestrate operation on the data path– Based on desired function and signalsDatapathControllerControl PointssignalsTopics since MidTerm I• Project– Clock domains, protocols, integration of digital subsystems– Controller design, interfaces, buffering, matching• Timing– propagation delays, setup, hold, critical path, fan-out, wires• Static RAM– 6T cell, organization (decode, cells, row, col mux, drive & sense)– shared data I/O, Read/Write Protocol, • Dynamic DRAM– 1T cell, organization (decoders, row buffers, refresh)– Multiplexed address, RAS, CAS, protocols (page, static col, …)• Number Systems– Integer, Fix Point, Floating Point– Unsigned, 2s comp, sign mag., 1s comp, excess. Operations• Arithmetic Circuits– Addition, Subtraction, Compare, Mulitply• Error detection, correction, coding– Parity, Hamming, SECDED, redundancy check, CRCMotivation• Data Transmission in asynchronous circuits– Handshaking– Oversampling• Design techniques– Timing diagram– Top-down design– Bubble-and-arc• Communication Protocol – RS232– one of the most heavily used standards ever developed for computing equipment.– Baud rate: 9600 ~ 56000 bpsKeypad & LCD screen• standard parts…Problem Specification (1)• Design two subsystems: – Transmitter» Takes input from a telephone-like keypad.» Sends a byte corresponding to the key over a single wire one bit at a time.– Receiver» Receives the serial data sent by the transmitter» Displays it on a small LCD screenProblem Specification (2)• RS232 protocol for formatting the data one the wire• The wire is normally high – quiescent value• A data begins with a start bit – low for one bit• 8 data bits w/ msb first• After the 8 bits, the wire must be high for at least one bit time before the next byte’s start bit – stop bit8 databitsstartbitstopbitUnderstanding the Specification (1)• Two devices will be completely asynchronous to each other.– The single wire will carry only “data”– The receiving side should be able to determine when a start bit is starting.– If sampling the wire once every bit time we may just miss the start bit between two high values.– We need to have a faster clock that will sample the wire faster than once every bit cycle.• Oversampling– sample multiple times during each bit time to make sure that we pick out the starting falling edge of each byte’s transmission. – Oversampling is a common technique in communication circuitsUnderstanding the Specification (2)• LCD device is asynchronous.– There is no clock.– We have asynchronous control signals• Robust and Modular– Need to make sure the data has been transmitted.– Data processing speeds are not the same.• Handshaking– Need to make sure your data has been transferred to the destination.– 1. Sender: Request– 2. Receiver: Request Acknowledged– 3. Sender: OK…– 4. Receiver: Work done!!AcknowledgeRequestDesign Techniques• Timing Diagram– Oversampling needs to pick up falling edge of input signal and interacts with counters.– Handshaking is between asynchronous circuits and synchronous circuits.– In general, timing diagram is very important in digital design.• Top Down & Bubble-and-arc Diagram– Top Down design: define larger block and break it into smaller blocks.– Bubble-and-arc for finite state machines.Implementation (1)ReceiverDisplayControlDisplay8ResetRClkRRxDRcvdDBAckRRS ECharRcvd8SenderSend8CharToSendKeyboardKeyboardDecode7ResetSClkSTxDAckS• Sender– Keyboard - input device– KeyboardDecode – decodes the signals from the keypad and turns them in to the appropriate character code for the button. Bridges KB and Sender domains.– Sender – takes the byte and serially transmits it over the single wire • Receiver– Display – LCD output– DisplayControl – gives data and controls to the LCD appropriately to get the corresponding character to show up on the screen. Bridges domain.– Reciever – observes the signal wire coming from the sender and determines when a byte has been received.Implementation (2)Keyboard (1)1234567890#*CommonRow 2Row 4Col 1Col 2Col 3Row 1Row 3RCKeyboard (2)Row XColumn YKey XYCommonKeypadKeyboardDecode• It decodes key presses into the 8-bit character code.• Four-cycle handshake – robust and modularvalid dataDataAckSSendSendAckSDataSenderSend8CharToSendKeyboardKeyboardDecode7ResetSClkSTxDAckSKeyboardDecode – Handshaking (1)• Handshake between the KeyboardDecode block and the Sender block.• Send is raised first.• Raise AckS in response.• This in turn will be seen by the original block that is now assured its raising of the Send output has been observed. It then lowers Send• Lower AckS.valid dataDataAckSSendKeyboardDecode – Handshaking (2)• Either block can take more time to do what it needs to do by delaying when it raises or lowers its signal.• If data is being sent along with the handshake, the data should be held constant from when Send is raised to when the acknowledgement, via AckS, is received.valid dataDataAckSSendKeyboardDecode – Handshaking (3)• What happens if a second key is pressed?valid dataDataAckSSendKeyboardDecodeFFenDOutKeyPressed & !AckS8’b001100018’b00110010…….8’b00100011FFenSendResetS | AckSKeyPressed & !AckSrsetKeyboardDecode – VerilogModule KeyboardDecode (ClkS, ResetS, R1, R2, R3, R4,C1, C2, C3, AckS, Send, DOut);input ClkS, ResetS, AckS;input R1, R2, R3, R4, C1, C2, C3;output Send;output [7:0] DOut;reg [7:0] DOut;reg send;wire KeyPressed;assign KeyPressed = (R1 | R2 | R3 | R4) & (C1 | C2 | C3);KeyboardDecode


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Berkeley COMPSCI 150 - Lec 19 – Putting it together

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