EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3In the News ...Multiplication“Shift and Add” MultiplierSlide 5Array MultiplierCarry-save AdditionSlide 8Array Multiplier with Carry-SaveSlide 10Slide 11CL Circuits from ManoMagnitude ComparatorMultiplexors RevisitedDecodersHierarchical DecodersEncodersSpring 2002 EECS150 - Lec12-cl3Page 1EECS150 - Digital DesignLecture 12 - Combinational Logic Circuits Part 3March 4, 2002John WawrzynekSpring 2002 EECS150 - Lec12-cl3Page 2In the News ...Spring 2002 EECS150 - Lec12-cl3Page 3Multiplicationa3a2a1a0Multiplicandb3b2b1b0MultiplierX a3b0a2b0a1b0a0b0 a3b1a2b1a1b1a0b1 Partial a3b2a2b2a1b2a0b2 productsa3b3a2b3a1b3a0b3 . . . a1b0+a0b1a0b0 ProductMany different circuits exist for multiplication.Each one has a different balance between speed (performance) and amount of logic (cost).Spring 2002 EECS150 - Lec12-cl3Page 4“Shift and Add” Multiplier•Sums each partial product, one at a time.•In binary, each partial product is shifted versions of A or 0.Control Algorithm: 1. P 0, A multiplicand, B multiplier 2. If LSB of B==1 then add A to P else add 0 3. Shift [P][B] right 1 4. Repeat steps 2 and 3 n-1 times. 5. [P][B] has product.Bn - b i t s h i f t r e g i s t e r sPAn - b i t r e g i s t e r+010 n - b i t a d d e r•Cost n, = n clock cycles.•What is the critical path for determining the min clock period?Spring 2002 EECS150 - Lec12-cl3Page 5“Shift and Add” MultiplierSigned Multiplication:Remember for 2’s complement numbers MSB has negative weight:ex: -6 = 110102 = 0•20 + 1•21 + 0•22 + 1•23 - 1•24 = 0 + 2 + 0 + 8 - 16 = -6•Therefore for multiplication:a) subtract final partial productb) sign-extend partial products•Modifications to shift & add circuit:a) adder/subtractorb) sign-extender on P shifter register 112022nniNiixxXSpring 2002 EECS150 - Lec12-cl3Page 6Array Multiplier0 000 b0b1b3b2a00p0a10p1a20p2a30p3p4p5p6p7Generates all partial products simultaneously.Each row: n-bit adder with AND gates.FAaicarryinsum outsum inbjWhat is the critical path?Delay ?, cost ?Spring 2002 EECS150 - Lec12-cl3Page 7Carry-save Addition•Speeding up multiplication is a matter of speeding up the summing of the partial products.•“Carry-save” addition can help.•Carry-save addition passes (saves) the carries to the output, rather than propagating them.•Example: sum three numbers,310 = 0011, 210 = 0010, 310 = 0011 310 0011+ 210 0010 c 0100 = 410 s 0001 = 110 310 0011 c 0010 = 210 s 0110 = 610 1000 = 810carry-save addcarry-save addcarry-propagate add•In general, carry-save addition takes in 3 numbers and produces 2.•Whereas, carry-propagate takes 2 and produces 1.•With this technique, we can avoid carry propagation until final additionSpring 2002 EECS150 - Lec12-cl3Page 8Spring 2002 EECS150 - Lec12-cl3Page 9Array Multiplier with Carry-SaveSpring 2002 EECS150 - Lec12-cl3Page 10Spring 2002 EECS150 - Lec12-cl3Page 11Spring 2002 EECS150 - Lec12-cl3Page 12CL Circuits from Mano•Magnitude Comparator•Multiplexors (revisited)•Decoders–basic–hierarchical•Encoders–standard–Priority EncoderSpring 2002 EECS150 - Lec12-cl3Page 13Magnitude Comparator•We studied magnitude comparators in CS61c as part of the MIPS processor design.•What was that method? Why that then and not now?(A>B) = A3B’3 + x3A2B’2 + x3x2A1B’1 + x3x2x1A0B’0(A=B) = x3x2x1x0(A>B) = A’3B3 + x3A’2B2 + x3x2A’1B1 + x3x2x1A’0B0Spring 2002 EECS150 - Lec12-cl3Page 14Multiplexors Revisited•Basic AND/OR form•NAND/NAND•tristate buffer based•transmission gate based•hierarchical•decoder based–delay analysisSpring 2002 EECS150 - Lec12-cl3Page 15DecodersSpring 2002 EECS150 - Lec12-cl3Page 16Hierarchical DecodersSpring 2002 EECS150 - Lec12-cl3Page 17Encoders•Generates binary code at output corresponding to input code.•Example: one-hot to binary encoder. (Opposite of decoder)a b c d x y1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1•Priority Encoder:–If two or more inputs are equal to 1 at the same time the input with the highest “priority” will take precedence.•Example:a b c d x y V0 0 0 0 - - 01 0 0 0 0 0 0- 1 0 0 0 1 1- - 1 0 1 0 1- - - 1 1 1 1•“V” is the valid signal, “d” has highest
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