Time TableEECS150: Homework 8, Power and TimingUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 Time TableASSIGNED Friday, March 13thDUE Friday, March 20that 2pmHomework submission will only be through SVN. Email submissions will not be ac-cepted!1. You are given a static CMOS 6-input NAND gate whose output is driving a capacitance Cload.The gate is powered by a supply voltage VDDand is part of a synchronous circuit running at somefrequency f. Ignore any static (leakage) currents for this problem.(a) As a function of the given variables, how much energy is dissipated by the circuit each timethe output m akes a 0 → 1 transition? What about a 1 → 0 transition? Is any energy used ifthe output stays the same?(b) As a function of the given variables, what is the average power dissipated by this circuit if, onany given cycle, the probability that the output will make either a 0 → 1 or 1 → 0 transitionis α?(c) Suppose each input has a 50% chance of switching (either a 0 → 1 or 1 → 0 transition) eachcycle. Find a numerical value for α, the probability that the output of the gate switches onany given cycle.(d) Let Cload= 100f F , VDD= 1.2V , and f = 2GHz. Using the α you found in the previouspart, numerically calculate the average power dissipated by this gate.(e) Suppose instead that we were analyzing a 6-input XOR gate being subjected to the exactsame conditions. Would you expect its average power consumption be bigger, smaller, orequal to that of the 6-input NAND gate? Why?2. Your boss at chipsRus.com asks you to determine the average node activity factor α of a particularchip. In the lab you find:• A power supply for powering the chip at some particular voltage V.• A clock generator to output some frequency f.• A current meter for determining its average current consumption while running I.• A pattern generator for applying typical input patterns to the chip while running.Additionally you:• Call up the designer of the chip and leave voice mail asking her the number of internal nodesin the chip n.• and the average node capacitance C.(a) Derive a formula you can use for finding α.1(b) The designer calls back and says that the chip has 1 Million nodes, and each node has anaverage capacitance of 10fF. You go to the lab and measure the average current consumptionto be 0.25 A at 2 V and 100 MHz. What is the value of α?(c) Suppose you turn off your clock generator and find that the circuit is still drawing a hefty0.10 A at 2 V. Explain what is happening and modify the activity factor α that you foundearlier to account for this.3. Consider a CMOS AND gate implemented as a NAND gate followed by an inverter. Assume theinverter propagation delay is defined as follows (units in picoseconds):τp= 50 + 100 · fWhere f is the fanout of the inverter, expressed in number of transistor gate inputs. For example,inverters contribute 2 to f and one input of a 2-input NOR gate contributes 2. Note to peoplewho have taken EE141: this is not the f =CoutCindefinition of fanout used in EE141.Assume this inverter has the same propagation delay for both 0 → 1 and 1 → 0 transitions.The NAND gate propagation delay is expressed as (in ps):τp0→1= 100 + 75 · fτp1→0= 100 + 125 · fFor the 0 → 1 and 1 → 0 transitions, respectively. Write the expressions for the 0 → 1 and 1 → 0propagation delays of the AND gate.4. Consider the circuit given in Figure 1.Figure 1 Interesting Circuit• The propagation delay (for both high-to-low and low-to-high transitions) of the inverters areτp= 50 + 100 · f (in ps).• The propagation delay (for both kinds of transitions) of the NAND gates are τp= 100+150· f(in ps).• The flip-flop tsetup= tclk−q= 50ps.• There is no clock skew• There are three instances of this circuit cascaded together, we are fo c using our analysis onthe middle one.(a) Mark the critical path in the diagram(b) List the gates of the critical path (by gate number) in the order of signal propagation andtheir associated delays. Remember to account for the fanout.(c) What is the minimum clock period T for correct operation of this circuit?5. Consider an n-bit ripple-carry adder implemented using the full-adder circuit given in DDCAFigure 4.8.2(a) Find the critical path through this adder and the input combination that triggers it.(b) Count the number of gate delays (i.e. if a signal passes through an XOR gate, add 1 to itsgate delay) in the critical path as a function of n.6. Figure 2 shows a Schmoo plot for a processor.Figure 2 Schmoo plot of a processorIn this problem, the processor characterized by the Schmoo plot is used in a system along withsupport components that use K Watts of power. For example, in a laptop, the support chips mightconsume 2 Watts. For this system, K = 2.When the processor is running, the support comp onents must stay on. A CPU instruction maybe used to turn the processor and the support components off. When off, the processor and thesupport components both use no power at all.(a) Different systems may have different values of K. For example, the support chips for a laptopdesign may consume 2 Watts (K = 2), while support chips for a desktop design may consume7 Watts (K = 7).A program runs twice as fast at Operating Point P (shown in Figure 2) than at OperatingPoint Q. The last instruction of the program turns off power to the processor and its supportchips.i. For what range of values for K does Operating Point P use the lowest amount of energyto run the program?ii. For what range of values for K does Operating Point Q use the lowest amount of energyto run the program?iii. For what range of values for K do Operating Points P and Q use the same amount ofenergy?3(b) A program runs twice as fast at Operating Point P than at Op e rating Point R. The lastinstruction of the program turns off power to the processor and its support chips.i. For what range of values of K does Operating Point P use the lowest amount of energyto run the program?ii. For what range of values of K does Operating Point R use the lowest amount of energyto run the program?iii. For what range of values for K do Operating Points P and R use the same amount
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