Time TableObjectivesPhilosophyGeneral Project TipsProject DescriptionMIPS150 ProcessorSerial InterfaceFrame BufferColor MapVideo InterfaceLine Drawing EngineOptimizationsExtra CreditProject AdministrationDesign ReviewsCheckpointsStyle: Organization, Design and the Project ReportFinal CheckoffExtra CreditEarly CheckoffAdditional Functionality-(Extra Credit)A.K.A. the ``Late Policy.''Project GradingProject TimelineCheckpoint 1: MIPS150 ProcessorCheckpoint 2: Serial InterfaceCheckpoint 3: Frame BufferCheckpoint 4: Vector Accelerator EngineCheckpoint 5: OptimizationsEarly CheckoffFinal CheckoffSVN Submission ProcedureFinal Checkoff ProcedureEECS150: Spring 2009 Project, MIPS150UC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer ScienceRevision A1 Time TableASSIGNED Friday, February 26thDUE Week 16: May, 8th, 11:59pm2 ObjectivesThe primary goal of this project is to familiarize EECS150 students with the metho ds and tools of digitaldesign. However, in order to make the project both interesting and useful, we will guide you throughthe design and implementation of a miniature, yet complete, digital system. This semester, the digitalsystem we are having you design will consist of a simple 3-stage CPU implementing a subset of the MIPSISA. In addition to this, you will implement a portion of a very real DVI video interface and a simplegraphics accelerator capable of rendering lines. Figure 1 shows an abstract view of how the componentsin this system are brought together to form a system. Getting a functional implementation running isand will be your primary goal. To better e xpose you to real design decisions and tradeoffs, however, weare requiring that you optimize your design for area (FPGA resource utilization) given a certain clockfrequency.Figure 1 MIPS150You will use Verilog HDL to implement this system, targeting a Xilinx XUPv5 platform (poweredby a Virtex 5 LX110T FPGA). You will use industry-standard CAD tools including Mentor Graphics’1ModelSim, Synopsis’ SynplifyPro, and the Xilinx ISE toolflow to map your Verilog to actual resources onthe FPGA. The project will give you experience designing RTL, resolving hazards in a simple pipeline,building interfaces, and teach you how to approach system-level optimization.In tackling these challenges, your first step will be to map our high level specification to a designwhich can be translated into a hardware implementation. After that, you will produce and debug thatimplementation. These first steps can potentially take significant time if you have not thought out yourdesign prior to trying implementation. After you have built a working implementation, the next stepwill be optimizing it for area (cost, resource use) on the target FPGA. You will be expected to producea relatively minimal circuit, implementing the required functionality, given a clock fixed at a certainfrequency. At the end of this sec ond phase (optimization, post implementation), you will have a greaterunderstanding for the development process of digital hardware.As in previous semesters, your EECS150 project is possibly the largest project you have faced so far.Good time management and good design will help you succeed in this course.2.1 PhilosophyThis document is meant to describe a high-level specification for the project and its associated s upporthardware. You can also use it to help lay out a plan for completing the project. As with any design youwill encounter in the professional world, we are merely providing a framework within which your projectmust fit. Unlike other college classes we will not tell you exactly what to write or how todesign your project.You should consider the TAs a source of direction and clarification, but it is up to you to producea fully functional design targeting the XUPv5 boards. We will attempt to help, when possible, butultimately the burden of designing and debugging your solution lies on you.In the end, what counts is having a well-implemented, bug free and optimized project by May, 8th,11:59pm. Due on May, 8th, 11:59pm is everything describ e d and required in the project specificationsthat you will be getting in the coming weeks. This semester, you are able to receive some extra credit bycompleting your project ahead of schedule (Early Checkoff. This is optional and is described in detailin Section4.5.1. There is also the opportunity to extend our framework with additional functionality forextra credit. This more traditional extra credit is described in Section 4.5.2.2.2 General Project TipsMake sure to use top-down design methodologies in this project. We began by taking the problem ofdesigning a basic computer system, modularizing it into distinct parts, and then refining those partsinto manageable checkpoints. You should take this scheme 1 step further: we have given you eachcheckpoint, so break each into smaller and manageable pieces. If you follow this guideline, and ourinterface specifications, you should be able to split the project up between you and your partner and fora more efficient partnership.As with many engineering disciplines, digital design has a normal development cycle. In the norm,after modularizing your design, your strategy should roughly resemble the following steps:Design your modules well, make sure you understand what you want before you begin to code.Code exactly what you designed; do not try to add features without redesigning.Simulate thoroughly; writing a good testbench is as much a part of creating a module as actuallycoding it.Debug completely; anything which can go wrong with your implementation will.Document your project thoroughly, as you go. Your design review documents will help, but youshould never forget to comment your Verilog and to keep your diagrams up to date. Aside from the finalproject report (you will need to turn in a report documenting your project), you can use your designdocuments to help the debugging process. Finish the required features first. Attempt extra features aftereverything works well. If your submitted project does not work by the final deadline, you willnot get any credit for any extra credit features you have implemented.23 Project De script io nThe project, as has been done in past semesters, will be divided into checkpoints. This section willsummarize the content of the checkpoint documents released with each project checkpoint. It is thecomplete, high-level project specification for each checkpoint. For more detail please refer
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