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Berkeley COMPSCI 150 - Lecture 7 - Finite State Machines 1

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1Spring 2003 EECS150 - Lec07-FSM1Page 1EECS150 - Digital DesignLecture 7 - Finite State Machines 1February 11, 2003John WawrzynekSpring 2003 EECS150 - Lec07-FSM1Page 2Parity Checker ExampleA string of bits has “even parity” if the number of 1’s in the string is even.• Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd:• Can you guess a circuit that performs this function?ParityCheckerINOUTbit stream0 if even parity1 if odd parityexample: 0 0 1 1 1 0 1 even even odd even odd odd evenCLKtimeCLKINOUT2Spring 2003 EECS150 - Lec07-FSM1Page 3Formal Design Process • “State Transition Diagram”– circuit is in one of two states.– transition on each cycle with each new input, over exactly one arc (edge).– Output depends on which state the circuit is in.ParityCheckerINOUTbit stream0 if even parity1 if odd parityexample: 0 0 1 1 1 0 1 even even odd even odd odd evenCLKtimeSpring 2003 EECS150 - Lec07-FSM1Page 4Formal Design Process• State Transition Table:• Invent a code to represent states:Let 0 = EVEN state, 1 = ODD statepresent nextstate OUT IN stateEVEN 0 0 EVENEVEN 0 1 ODDODD 1 0 ODDODD 1 1 EVENpresent state (ps) OUT IN next state (ns)0 0 0 00 0 1 11 1 0 11 1 1 0Derive logic equations from table (how?):OUT = PSNS = PS xor IN3Spring 2003 EECS150 - Lec07-FSM1Page 5Formal Design Process• Circuit Diagram:– XOR gate for ns calculation– DFF to hold present state– no logic needed for outputLogic equations from table:OUT = PSNS = PS xor INnsps• Review of Design Steps:1. Circuit functional specification2. State Transition Diagram3. Symbolic State Transition Table4. Encoded State Transition Table5. Derive Logic Equations6. Circuit DiagramFFs for stateCL for NS and OUTSpring 2003 EECS150 - Lec07-FSM1Page 6Finite State Machines (FSMs)• FSM circuits are a type of sequential circuit:– output depends on present andpast inputs• effect of past inputs is represented by the current state• Behavior is represented by State Transition Diagram:– traverse one edge per clock cycle.4Spring 2003 EECS150 - Lec07-FSM1Page 7FSM Implementation• FFs form state register• number of states ≤ 2number of flip-flops• CL (combinational logic) calculates next state and output• Remember: The FSM follows exactly one edge per cycle.Spring 2003 EECS150 - Lec07-FSM1Page 8Combination Lock Example• Used to allow entry to a locked room:2-bit serial combination. Example 01,11:1. Set switches to 01, press ENTER2. Set switches to 11, press ENTER3. OPEN is asserted (OPEN=1).If wrong code, ERROR is asserted (after second combo word entry).Press Reset at anytime to try again.5Spring 2003 EECS150 - Lec07-FSM1Page 9AnnouncementsSpring 2003 EECS150 - Lec07-FSM1Page 10Combination Lock Example• Used to allow entry to a locked room:2-bit serial combination. Example 01,11:1. Set switches to 01, press ENTER2. Set switches to 11, press ENTER3. OPEN is asserted (OPEN=1).If wrong code, ERROR is asserted (after second combo word entry).Press Reset at anytime to try again.6Spring 2003 EECS150 - Lec07-FSM1Page 11Combinational Lock STDSpring 2003 EECS150 - Lec07-FSM1Page 12Symbolic State Transition TableRESET ENTER COM1 COM2 Preset State Next State OPEN ERROR0 0 * * START START 0 0010* START BAD100011* START OK10000**OK1 OK10001* 0OK1 BAD20001* 1OK1 OK2000***OK2 OK2100 0 * * BAD1 BAD1 0 00 1 * * BAD1 BAD2 0 00 * * * BAD2 BAD2 0 11**** START00Decoder logic for checkingcombination (01,11):7Spring 2003 EECS150 - Lec07-FSM1Page 13Encoded ST TableENTERCOM1COM2PS2PS1PS0NS2NS1NS0000000000001000000010000000011000000100000100101000100110000001111000001000001001001001001010001001011001001100001101110001101101001011111001011000011011001011011010011011011011011100011011101011011110011011111011011000100100001100100010100100011100100100100101101100101110100101111100101000101101001101101010101101011101101100101101101101101110101101111101101• Assign states:START=000, OK1=001, OK2=011BAD1=100, BAD2=101• Omit reset. Assume that primitive flip-flops has reset input.• Rows not shown have don’t cares in output. Correspond to invalid PS values.• What are the output functions for OPEN and ERROR?00 01 11 1000101110cdefab = 1000 01 11 1000101110ab = 1100 01 11 1000101110ab = 0100 01 11 1000101110ab = 0000 01 11 1000101110cdefab = 1000 01 11 1000101110ab = 1100 01 11 1000101110ab = 0100 01 11 1000101110ab = 0000 01 11 1000101110cdefab = 1000 01 11 1000101110ab = 1100 01 11 1000101110ab = 0100 01 11 1000101110ab = 00NS2 NS1 NS0Spring 2003 EECS150 - Lec07-FSM1Page 14FSM Implementation Notes• General FSM form:• All examples so far generate output based only on the present state:• Commonly name Moore Machine(If output functions include both present state and input then called a Mealy Machine)8Spring 2003 EECS150 - Lec07-FSM1Page 15State Encoding• In general:# of possible state = 2# of FFs• However, often more than log2(# of states) FFs are used, to simplify logic at the cost of more FFs.• Extreme example is one-hot state encoding.• One-hot encoding of states.• One FF per state.• Simple design procedure.• Circuit matches state transition diagram.• Can be costly for FSMs with large number of states Spring 2003 EECS150 - Lec07-FSM1Page 16One-hot encoded FSM• Even Parity Checker Circuit:• In General:• FFs must be initialized for correct operation (only one 1)9Spring 2003 EECS150 - Lec07-FSM1Page 17One-hot encoded combination


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Berkeley COMPSCI 150 - Lecture 7 - Finite State Machines 1

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