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Berkeley COMPSCI 150 - Lec 18 – Error Coding

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EECS 150 - Components and Design Techniques for Digital Systems Lec 18 – Error CodingOutlineOur beautiful digital world….In the real world …The ChallengeDefinitionsError Correction Codes (ECC)Correcting Code ConceptSimple Error Detection Coding: ParityRecall: Boolean cubesSingle Error DetectionError correctionSECDED ideaHamming Error Correcting CodeExample: 8 bit SECHamming Code ExampleInteractive QuizSlide 18AnnouncementsConcept: Redundant CheckExample: TCP ChecksumDetecting burst errorsExample: Ethernet CRC-32Linear Feedback Shift Registers (LFSRs)4-bit LFSRApplications of LFSRsCRC conceptGalois Fields - the theory behind LFSRsGalois Fields - The theory behind LFSRsSo what about division (mod)Polynomial divisionCRC encodingCRC decodingSlide 34Galois Fields – PrimitivesPrimitive PolynomialsBuilding an LFSR from a Primitive PolyGenerating PolynomialsSummaryEECS 150 - Components and Design Techniques for Digital Systems Lec 18 – Error Coding David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs15010/25/2007EECS 150, Fa07, Lec18-error2Outline•Errors and error models•Parity and Hamming Codes (SECDED)•Errors in Communications•LFSRs•Cyclic Redundancy Check (CRC)10/25/2007EECS 150, Fa07, Lec18-error3Our beautiful digital world….•The real world has continuous electrical signals•In the real world, electrons keep flowing•In the real world, things take time•We’ve designed circuits to create logical gates that behave like boolean operators•We designed storage elements that hold their logical value•We’ve developed a synchronous timing methodology so that values appear to change on clock edges–Acyclic combinational logic and storage elements–Clock cycle > worst propagation delay + setup10/25/2007EECS 150, Fa07, Lec18-error4In the real world …•_ _ i t happens !•Alpha particles flip bits in memory•Electrostatics zap wires•Electromagnetic interference clobbers communication•…10/25/2007EECS 150, Fa07, Lec18-error5The Challenge•How do we design digital systems that behave correctly even in the presence of errors?10/25/2007EECS 150, Fa07, Lec18-error6Definitions•An error in a digital system is the corruption of data from its correct value to some other value.•An error is caused by a physical failure.–Temporary or permanent•The effects of failures are predicted by error models.•Example: independent error model –a single physical failure is assumed to affect only a single bit of data – a single error–Multiple failures may cause multiple errors»Much less likely10/25/2007EECS 150, Fa07, Lec18-error7Error Correction Codes (ECC)•Memory systems generate errors (accidentally flipped-bits)–DRAMs store very little charge per bit–“Soft” errors occur occasionally when cells are struck by alpha particles or other environmental upsets.–Less frequently, “hard” errors can occur when chips permanently fail.–Problem gets worse as memories get denser and larger•Where is “perfect” memory required?–servers, spacecraft/military computers, ebay, …•Memories are protected against failures with ECCs•Extra bits are added to each data-word–used to detect and/or correct faults in the memory system–in general, each possible data word value is mapped to a unique “code word”. A fault changes a valid code word to an invalid one - which can be detected.10/25/2007EECS 150, Fa07, Lec18-error8Correcting Code Concept•Detection: bit pattern fails codeword check•Correction: map to nearest valid code wordSpace of possible bit patterns (2N)Sparse population of code words (2M << 2N) - with identifiable signatureError changes bit pattern to non-code10/25/2007EECS 150, Fa07, Lec18-error9Simple Error Detection Coding: Parity•Each data value, before it is written to memory is “tagged” with an extra bit to force the stored word to have even parity:•Each word, as it is read from memory is “checked” by finding its parity (including the parity bit). b7b6b5b4b3b2b1b0p+b7b6b5b4b3b2b1b0p+c•A non-zero parity indicates an error occurred:–two errors (on different bits) is not detected (nor any even number of errors)–odd numbers of errors are detected.•What is the probability of multiple simultaneous errors?10/25/2007EECS 150, Fa07, Lec18-error101-cubeX0 1Recall: Boolean cubes•Neighbors differs by one bit•The Hamming Distance between two values is the number of bits that must be changed to convert one into the other.•Parity – code words have minimum distance > 12-cubeXY110001103-cubeXYZ0001111014-cubeWXYZ000011111000011110/25/2007EECS 150, Fa07, Lec18-error11Single Error Detection•N information bits + 1 parity bit–2N code words with minimum distance 2.•What if we added another parity bit on the N+1 bits?–min-distance-3 code => detects double bit errors•What do you do if an error is detected?•What would you need to know to correct the error?10/25/2007EECS 150, Fa07, Lec18-error12Error correction•When we receive an non code word, we correct the error by locating the nearest code word–Extremely likely to have been the one that was transmitted•Example: distance 3 code => single error will produce a value at distance 1 from the original and distance 2 or greater from all the rest.•2c+1 code can correct errors up to c bits•2c+d+1 code can correct errors up to c bits and detect errors in up to d additional bits•SECDED most common4-cubeWXYZ000011111000011110/25/2007EECS 150, Fa07, Lec18-error13SECDED idea•Add enough parity bits that with a single error the parity sequence gives the “address” of the bit that flipped!•Add one more bit for parity of the whole thing•How many bits does it take10/25/2007EECS 150, Fa07, Lec18-error14Hamming Error Correcting Code•Use more parity bits to pinpoint bit(s) in error, so they can be corrected.•Example: Single error correction (SEC) on 4-bit data –use 3 parity bits, with 4-data bits results in 7-bit code word–3 parity bits sufficient to identify any one of 7 code word bits–overlap the assignment of parity bits so that a single error in the 7-bit work can be corrected•Procedure: group parity bits so they correspond to subsets of the 7 bits:–p1 protects bits 1,3,5,7 (bit 1 is on)–p2 protects bits 2,3,6,7 (bit 2 is on)–p3 protects bits 4,5,6,7 (bit 3 is on)1 2 3 4 5 6 7p1 p2 d1 p3 d2 d3


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Berkeley COMPSCI 150 - Lec 18 – Error Coding

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