11.2.1CS150 Newton/PisterOutlinem Last time:Ô Introduction to Computer OrganizationÔ ControlÔ DatapathÔ I/O InterfaceÔ Bussing Strategiesm This lecture:Ô Deriving the State Diagram & Datapath (Cont.)Ô Mapping the Datapath onto Control11.2.2CS150 Newton/PisterFinite State Machines for Simple CPUsState Diagram and Datapath DerivationProcessor Specification:Instruction Format:Memory Interface:Load from memory: Mem[XXX] → AC;Store to memory: AC → Mem[XXX];Add from memory: AC + Mem[XXX] → AC;Branch if accumulator is negative: AC < 0 ⇒ XXX → PC;15 14 130Op Code00 = LD 01 = ST 10 = ADD 11 = BRNAddressM A RM B R1416[0:2 -1]<15:0>14MemoryRequest Read/Write Wait11.2.3CS150 Newton/PisterFinite State Machines for Simple CPUsDeriving the State Diagram and DatapathFirst pass state diagram:ResetInstruction FetchOperation DecodeLDSTADDBRNOperation Execution11.2.4CS150 Newton/PisterReset/0 → PCReset/ PC → MAR, PC + 1 → PCReset/Wait/Wait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/Wait/Mem → MBRWait/MBR → IRRESIF1IF2IF0Deriving the State Diagram and DatapathAssume Synchronous Mealy Machine: Transitions associated with arcs rather than statesReset State (State 0)and Instruction FetchSequenceReset State (State 0)and Instruction FetchSequenceOn Reset: zero the PC Mem Request unasserted Mem asserts Wait signal11.2.5CS150 Newton/PisterReset/0 → PCReset/ PC → MAR, PC + 1 → PCReset/Wait/Wait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/Wait/Mem → MBRWait/MBR → IRRESIF1IF2IF0Deriving the State Diagram and DatapathAssume Synchronous Mealy Machine: Transitions associated with arcs rather than statesReset State (State 0)and Instruction FetchSequenceReset State (State 0)and Instruction FetchSequenceOn Reset: zero the PC Mem Request unasserted Mem asserts Wait signalInstruction Fetch: issue read request 4 cycle handshake on Wait signal11.2.6CS150 Newton/PisterDeriving the State Diagram and DatapathAssume Synchronous Mealy Machine: Transitions associated with arcs rather than statesReset State (State 0)and Instruction FetchSequenceReset State (State 0)and Instruction FetchSequenceOn Reset: zero the PC Mem Request unasserted Mem asserts Wait signalInstruction Fetch: issue read request 4 cycle handshake on Wait signalNote: No explicit mention of the busses being used to implement register transfers!Reset/0 → PCReset/ PC → MAR, PC + 1 → PCReset/Wait/Wait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/Wait/Mem → MBRWait/MBR → IRRESIF1IF2IF011.2.7CS150 Newton/PisterDeriving the State Diagram and DatapathOperation Decode StateFour Way Next State Branch based on opcode bitsIR<15:14>=0001 1011LD0ST0AD0 BR0OD11.2.8CS150 Newton/PisterIR<15:14>=00/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/MBR → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODLD0LD1LD2RESDeriving the State Diagram and DatapathExecution SequencesLoad Sequencelike IFetch, except thatoperand address comesfrom IR and data shouldbe loaded into AC11.2.9CS150 Newton/PisterIR<15:14>=00/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/MBR → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODLD0LD1LD2RESDeriving the State Diagram and DatapathExecution SequencesLoad Sequencelike IFetch, except thatoperand address comesfrom IR and data shouldbe loaded into AC11.2.10CS150 Newton/PisterIR<15:14>=00/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/MBR → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODLD0LD1LD2RESDeriving the State Diagram and DatapathExecution SequencesLoad Sequencelike IFetch, except thatoperand address comesfrom IR and data shouldbe loaded into AC11.2.11CS150 Newton/PisterDeriving the State Diagram and DatapathExecution SequencesLoad Sequencelike IFetch, except thatoperand address comesfrom IR and data shouldbe loaded into ACIR<15:14>=00/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/MBR → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODLD0LD1LD2RES11.2.12CS150 Newton/PisterIR<15:14>=01/ IR<13:0> → MAR, AC → MBRWait/ MAR → Memory, MBR → Memory, 0 → Read/Write, 1 → RequestWait/Wait/Wait/Wait/ 0 → Read/Write, 1 → Request, MAR → Memory, MBR → MemoryWait/ODST0ST1ST2RESDeriving the State Diagram and DatapathStore Execution SequenceMemory write sequence11.2.13CS150 Newton/PisterIR<15:14>=01/ IR<13:0> → MAR, AC → MBRWait/ MAR → Memory, MBR → Memory, 0 → Read/Write, 1 → RequestWait/Wait/Wait/Wait/ 0 → Read/Write, 1 → Request, MAR → Memory, MBR → MemoryWait/ODST0ST1ST2RESDeriving the State Diagram and DatapathStore Execution SequenceMemory write sequence11.2.14CS150 Newton/PisterIR<15:14>=01/ IR<13:0> → MAR, AC → MBRWait/ MAR → Memory, MBR → Memory, 0 → Read/Write, 1 → RequestWait/Wait/Wait/Wait/ 0 → Read/Write, 1 → Request, MAR → Memory, MBR → MemoryWait/ODST0ST1ST2RESDeriving the State Diagram and DatapathStore Execution SequenceMemory write sequence11.2.15CS150 Newton/PisterDeriving the State Diagram and DatapathIR<15:14>=10/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/ MBR + AC → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODAD0AD1AD2RESAdd Execution SequenceSimilar to Load sequence Add MBR, AC rather than simply transfer MBR to AC11.2.16CS150 Newton/PisterIR<15:14>=10/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/ MBR + AC → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODAD0AD1AD2RESDeriving the State Diagram and DatapathAdd Execution SequenceSimilar to Load sequence Add MBR, AC rather than simply transfer MBR to AC11.2.17CS150 Newton/PisterIR<15:14>=10/ IR<13:0> → MARWait/ MAR → Memory, 1 → Read/Write, 1 → RequestWait/Mem → MBRWait/ MBR + AC → ACWait/Wait/ 1 → Read/Write, 1 → Request, MAR → MemoryWait/ODAD0AD1AD2RESDeriving the State Diagram and DatapathSimilar to Load sequence Add MBR, AC rather than simply transfer MBR to AC11.2.18CS150 Newton/PisterIR<15:14>=10/ IR<13:0> → MARWait/ MAR →
View Full Document