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Berkeley COMPSCI 150 - Lab 2 Designing with Verilog

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EECS 150 Spring 2008 Lab 2UCB 1 2008UNIVERSITY OF CALIFORNIA AT BERKELEYCOLLEGE OF ENGINEERINGDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCEASSIGNED: Week of 2/4DUE: Week of 2/11, 10 minutes after start of your assigned lab section.Lab 2Designing with Verilog1.0 MotivationIn this lab you will learn how to express a circuit design in a HardwareDescription Language (HDL), namely Verilog. By creating two similar designs inbehavioral and structural verilog, you will get a chance to not only familiarize yourselfwith different styles of Verilog, but also with the ModelSim simulator.2.0 IntroductionTo support the creation of very efficient circuits, and as an effort to ease entry ofold designs, and importing designs from other environments, Verilog supports the use ofuniversally accessible primitive gates like and, or and not. In addition, it supportsdataflow and behavioral modeling, which allow the design of more efficient control.In this lab, you will investigate the use of the two primary kinds of Verilog:structural and behavioral. You will create two similar, simple modules. One module willbe specified in behavioral Verilog, where you will describe the function of the circuitsuccinctly and rely on the modeling and synthesis CAD tools to determine the exactcircuit. The other circuit will be written in structural Verilog, were you will describe thecircuit down to the gate level. The final piece of Verilog in this lab will be the testbench,which, though also written in behavioral Verilog, is a little different in that it cannot besynthesized. This is because it describes an artificial set of test stimulus rather than anactual circuit.3.0 PrelabPlease make sure to complete the prelab before you attend your lab section. Youwill not be able to finish this lab in 3 hrs otherwise!1. Read this handout thoroughly. Pay particular attention to Section 4.0Lab Procedure as it describes in detail the circuits you must create.2. Examine the Verilog provided for this week’s lab.a. Make sure you understand exactly how the Lab2Testbenchworks.3. Write all of your Verilog ahead of time.a. You should add more test cases to Lab2Testbench.v. You willnot get checked off for this lab without a more thorough testing ofyour modules.4. You will need the entire 3 hr lab to test and debug your Verilog!EECS 150 Spring 2008 Lab 2UCB 2 20084.0 Lab ProcedureSince we expect you to write your Verilog ahead of time, and Verilog is nothingmore than a bunch of standard text in a file with a *.v extension, you can do this part ofthe lab entirely from home in your favorite text editor (we recommend notepad). Oryou can come into the lab and use the tools there. For those of you who like maintaininga single Xilinx Project Navigator project for each lab, you can even create the projectahead of time and write your Verilog from within Project Navigator.Whatever editor you use to create your Verilog files, at some point you will needto add all of the Verilog files (including Lab2Top and Lab2Testbench) to a new XilinxProject Navigator project, or to a new ModelSim project, to test your code and get itchecked off.Remember to manage your Verilog, projects and folders well. Doing a poorjob of managing your files can cost you hours of rewriting code, if you accidentallydelete your files.4.1 Lab2TopIn this lab you will be building the two sub-modules of Lab2Top. Lab2Toptakes a string of 8-bit inputs and maintains both a running sum of the inputs using anAccumulator and the largest of the inputs using a PeakDetector. ThePeakSelect input to Lab2Top can be used to select which of these values appears atthe output Out.Below are: a high-level block diagram of Lab2Top, a table specifying its portsand their purposes and a hierarchy of the modules that you will need to build to completethis lab.OutSelectInLab3TopAccumulatorPeak DetectorMuxFigure 1: Lab2Top High Level Block DiagramSignal Width Dir DescriptionIn8 I The input valueOut8 OThe output value from either the PeakDetector orAccumulatorLab2TopEECS 150 Spring 2008 Lab 2UCB 3 2008Enable1 INotify Lab2Top to accept the current input at InPeakSelect1 ISelects the output form the PeakDetector when1’b1Clock1 I The Clock signalReset1 IReset both the Accumulator and thePeakDetectorTable 1: Port Specification for Lab2TopLab3TopStructural BehavioralAccumulatorBehavioralPeakDetectorStructuralReg8StructuralComp8 StructuralComp1StructuralFDCEPrimitiveGate PrimitivesFigure 2: Hierarchy of Modules4.2 Behavioral AccumulatorRegister+AccumulatorInEnableClockOutReset8888Figure 3: The AccumulatorLab2TopEECS 150 Spring 2008 Lab 2UCB 4 20081. In the text editor of your choice (we recommend notepad) create a filecalled Accumulator.v in which you will define a single module calledAccumulator.a. This module should have the ports listed in Table 2.b. Be sure to use good Verilog style. You’ll be graded on this!Signal Width Dir DescriptionIn8 I The input value to be added to the total outputOut8 O The sum of all previous input valuesEnable1 INotify the accumulator to add In to OutClock1 I The Clock signal, the output changes only on rising edgesReset1 IReset the output to 8’h00.Table 2: Port Specification for Accumulator2. Specify your module entirely in behavioral Verilog.a. Our solution takes 4 lines of behavioral Verilog (not countingdeclarations).b. You may not instantiate any other module within youraccumulator.c. You may wish to refer to the lab lecture slides for examples ofbehavioral Verilog.3. Types of Assignmenta. A blocking assignment is written as “=” and should be used incombinational logic.b. A non-blocking assignment is written as“<=” and should be usedfor sequential logic, namely anywhere you have an always @(posedge Clock)c. Note that these kinds of assignments refer only to always blocks.The assign keyword always requires a simple “=”.4. Reg vs. Registera. The keyword reg in Verilog names a location into which analways block can place a value. It does not create any kind ofregister, it is merely a poorly named artifact of days past.b. always @ (posedge Clock) implies a register. i. Any reg assigned using Non-blocking assignment (<=) inan always @ (posedge Clock) block will become aregister during synthesis.5. Test this module individuallya. You should be able


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Berkeley COMPSCI 150 - Lab 2 Designing with Verilog

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