EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements)Sequential CircuitsCross-coupled NOR gatesAsynchronous State Transition DiagramNand-gate based SR latchLevel-sensitive SR LatchD-latchFlip-flopsJ-K FFJ-K Flip-flop from D-FFToggle Flip-flop from D-FFStorage Element TaxonomyDesign Example with RS FFBit-serial adder with RS FFResets/presetsAdding Reset/PresetsSpring 2002 EECS150 - Lec14-seq1Page 1EECS150 - Digital DesignLecture 14 - Sequential Circuits I(State Elements)March 12, 2002John WawrzynekSpring 2002 EECS150 - Lec14-seq1Page 2Sequential CircuitsCircuit with feedba ck .•Examples:FSMD-type latchHow about CL logic with feedback but without register?•Sequential circuits exhibit either synchronous or asynchronous behavior:–Synchronous: “state” of the circuit changes at regular intervals controlled by a clock.–Asynchronous: state changes with changing inputs. No clock present or circuit doesn’t wait for it.Spring 2002 EECS150 - Lec14-seq1Page 3Cross-coupled NOR gates•If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch:•What happens if R or S or both become = 1?RS NOR00 101 010 011 0remember,RSQQ'01000 110Spring 2002 EECS150 - Lec14-seq1Page 4Asynchronous State Transition DiagramQQ'01QQ'10QQ'00?SR=00 SR=00SR=10SR=01SR=11SR=01SR=11SR=10SR=00SR=10SR=01SR Latch:SR Q00 hold01 010 111 indeterminateSpring 2002 EECS150 - Lec14-seq1Page 5Nand-gate based SR latchSpring 2002 EECS150 - Lec14-seq1Page 6Level-sensitive SR Latch•The input “C” works as an “enable” signal, latch only changes output when C is high.•usually connected to clock.•Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.Spring 2002 EECS150 - Lec14-seq1Page 7D-latchCompare to transistor version:Spring 2002 EECS150 - Lec14-seq1Page 8Flip-flopsSpring 2002 EECS150 - Lec14-seq1Page 9J-K FFJ K Q(t) Q(t+)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0holdresetsettoggle•Add logic to eliminate “indeterminate” action of RS FF.•New action is “toggle”•J = “jam”•K = “kill”Spring 2002 EECS150 - Lec14-seq1Page 10J-K Flip-flop from D-FFSpring 2002 EECS150 - Lec14-seq1Page 11Toggle Flip-flop from D-FFSpring 2002 EECS150 - Lec14-seq1Page 12Storage Element Taxonomy synchronous asynchronous level-sensitive edge-triggeredD-type n.a.JK-type n.a. n.a.RS-type “latch” “flip-flop” “latch”Spring 2002 EECS150 - Lec14-seq1Page 13Design Example with RS FF•With D-type FF state elements, new state iscomputed based on inputs & present state bits - reloaded each cycle.•With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits.•Example: bit-serial adder (LSB first)n - b i t s h i f t r e g i s t e rn - b i t s h i f t r e g i s t e r sscr e s e tRF AF FBAWith D-FF for carrySpring 2002 EECS150 - Lec14-seq1Page 14Bit-serial adder with RS FF•RS FF stores the carry:SRQab0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b ci ci+1 sCarry kill a’b’Carry generateabSpring 2002 EECS150 - Lec14-seq1Page 15Resets/presetsSpring 2002 EECS150 - Lec14-seq1Page 16Adding Reset/Presets•D-type flip-flop from latches:•Asynchronous reset in Flip-flop:Either inverter (or both) can be replaced by either NOR gate or NAND gate in the second latch of the flip-flop. The second input to the gate is connected to reset or preset signal. The choice of NOR versus NAND defines the sense of the reset/preset (active-high versus active-low). The choice which inverter to replace defines reset versus preset.•Synchronous reset:A similar procedure as above is applied to the first latch of the flip-flop. Additional logic is needed to synchronize the reset signal with the correct level of the clock.D-latch
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