Hardware Description LanguagesHDLsVerilogStructural ModelSimple behavioral modelSimple Behavioral ModelDriving a SimulationComplete SimulationComparator ExampleMore Complex Behavioral ModelHardware Description Languages vs. Programming LanguagesHardware Description Languages and Combinational LogicHardware Description Languages and Sequential LogicFlip-flop in VerilogMore Flip-flopsStructural View of an FSMBehavioral View of an FSMBehavioral View of an FSM (cont’d)Timer for Traffic Light ControllerComplete Traffic Light ControllerVerilog FSM - Reduce 1s exampleMoore Verilog FSM (cont’d)Mealy Verilog FSMSynchronous Mealy MachineCS 150 - Fall 2000 - Hardware Description Languages - 1Hardware Description LanguagesDescribe hardware at varying levels of abstractionStructural descriptionTextual replacement for schematicHierarchical composition of modules from primitivesBehavioral/functional descriptionDescribe what module does, not howSynthesis generates circuit for moduleSimulation semanticsCS 150 - Fall 2000 - Hardware Description Languages - 2HDLsAbel (circa 1983) - developed by Data-I/OTargeted to programmable logic devicesNot good for much more than state machinesISP (circa 1977) - research project at CMUSimulation, but no synthesisVerilog (circa 1985) - developed by Gateway (absorbed by Cadence)Similar to Pascal and CDelays is only interaction with simulatorFairly efficient and easy to writeIEEE standardVHDL (circa 1987) - DoD sponsored standardSimilar to Ada (emphasis on re-use and maintainability)Simulation semantics visibleVery general but verboseIEEE standardCS 150 - Fall 2000 - Hardware Description Languages - 3VerilogSupports structural and behavioral descriptionsStructuralExplicit structure of the circuitE.g., each logic gate instantiated and connected to othersBehavioralProgram describes input/output behavior of circuitMany structural implementations could have same behaviorE.g., different implementation of one Boolean functionWe’ll only be using behavioral Verilog in DesignWorksRely on schematic when we want structural descriptionsCS 150 - Fall 2000 - Hardware Description Languages - 4module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2);endmoduleStructural ModelCS 150 - Fall 2000 - Hardware Description Languages - 5module xor_gate (out, a, b); input a, b; output out; reg out; assign #6 out = a ^ b;endmoduleSimple behavioral modelContinuous assignmentdelay from input changeto output changesimulation register - keeps track ofvalue of signalCS 150 - Fall 2000 - Hardware Description Languages - 6module xor_gate (out, a, b); input a, b; output out; reg out; always @(a or b) begin #6 out = a ^ b; endendmoduleSimple Behavioral Modelalways blockspecifies when block is executed I.e., triggered by which signalsCS 150 - Fall 2000 - Hardware Description Languages - 7module stimulus (x, y); output x, y; reg [1:0] cnt; initial begin cnt = 0; repeat (4) begin #10 cnt = cnt + 1; $display ("@ time=%d, x=%b, y=%b, cnt=%b", $time, x, y, cnt); end #10 $finish; end assign x = cnt[1]; assign y = cnt[0];endmoduleDriving a Simulation2-bit vectorinitial block executed only once at startof simulationdirective to stop simulationprint to a consoleCS 150 - Fall 2000 - Hardware Description Languages - 8Complete Simulation Instantiate stimulus component and device to test in a schematicxyabzCS 150 - Fall 2000 - Hardware Description Languages - 9module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign #5 Equal = (A & B) | (~A & ~B); assign #3 Alarger = (A & ~B); assign #3 Blarger = (~A & B);endmodule Comparator ExampleCS 150 - Fall 2000 - Hardware Description Languages - 10module life (n0, n1, n2, n3, n4, n5, n6, n7, self, out); input n0, n1, n2, n3, n4, n5, n6, n7, self; output out; reg out; reg [7:0] neighbors; reg [3:0] count; reg [3:0] i; assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0}; always @(neighbors or self) begin count = 0; for (i = 0; i < 8; i = i+1) count = count + neighbors[i]; out = (count == 3); out = out | ((self == 1) & (count == 2)); endendmoduleMore Complex Behavioral ModelCS 150 - Fall 2000 - Hardware Description Languages - 11Hardware Description Languages vs. Programming LanguagesProgram StructureInstantiation of multiple components of the same typeSpecify interconnections between modules via schematicHierarchy of modules AssignmentContinuous assignment (logic always computes)Propagation delay (computation takes time)Timing of signals is important (when does computation have its effect)Data structuresSize explicitly spelled out - no dynamic structures No pointersParallelismHardware is naturally parallel (must support multiple threads)Assignments can occur in parallel (not just sequentially)CS 150 - Fall 2000 - Hardware Description Languages - 12Hardware Description Languages and Combinational LogicModules: specification of inputs, outputs, bidirectional, and internal signalsContinuous assignment: a gate's output is a function of its inputs at all times (doesn't need to wait to be "called")Propagation delay: concept of time and delay in input affecting gate outputComposition: connecting modules together with wiresHierarchy: modules encapsulate functional blocksSpecification of don't care conditions (accomplished by setting output to “x”)CS 150 - Fall 2000 - Hardware Description Languages - 13Hardware Description Languages and Sequential LogicFlip-FlopsRepresentation of clocks - timing of state changesAsynchronous vs. synchronousFSMsStructural view (FFs separate from combinational logic)Behavioral view (synthesis of sequencers)Data-paths = ALUs + registersUse of arithmetic/logical operatorsControl of storage elementsParallelismMultiple state machines running in parallelSequential don't caresCS 150 - Fall 2000 - Hardware Description Languages - 14module dff (clk, d, q);input clk, d;output q;reg q;always @(posedge clk)q = d;endmoduleFlip-flop in VerilogUse always block's sensitivity list to
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