ADC08161Final Project DescriptionIntroductionPutting Everything TogetherDetailsUser Interface DescriptionUniversity of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS 150 R. KatzFall 2000 N. ZhouFinal Project DescriptionIntroductionFor the finial project you are expected to use the FPGA board to build a design that performs two basic functions:a) Take digitized audio samples as input and send them to other designs across a shared wire.b) Receive audio samples generated by other stations from the shared wire and output the samples to a digital to analog converter.Form the four check-off points you should have gained a pretty good understanding of how to design the different component for the interfaces needed for the final project. This involves using the SRAM the make a FIFO for buffering information, using the ADC and DAC to convert from analog to digital and vise versa, converting parallel data into serial from with the UART, and building a protocol for sharing the wire with other designs.Putting Everything TogetherAs you have learned from earlier the simple theory of operation for the final project is:Audio Transmission.a) Audio input from the ADC is sampled at a 2KHz interval. Each sample is represented as a 8bit unsigned integer.b) The input audio is buffered in the SRAM by using a FIFO mechanism. This is done because due to the nature of the shared wire we cannot guarantee that your design will get access to it to transmit the current packet before more bytes of audio are sampled.c) Audio bytes stored in the FIFO will be packed together to form a packet.d) When the wire becomes available for transmission as described by the network protocol and apacket is ready for transmission, the packet is sent across the shared wire to the other stations that are attached to the shared wire.Audio Reception.a) As described in checkpoint 4. Each design attached to the shared wire will receive all the packets that are sent across the wire, including the ones that from itself.b) When a packet arrives it will need to be checked to see whether it is meant for the design that received it, if not then the packet is ignored. The check is performed by matching the destination field in the packet with the station ID of the design. (Note the station ID of particular design is just the source field from the dip switches)c) Once it is established that the packet is meant for this particular design, the data in the packet will be buffered in another FIFO. The reason for buffering is pretty much the same as before, for a short amount of time, data could be coming in at a higher rate than the 2KHz rate that you are outputting to the DAC.d) Once the buffer fill up to a certain depth, (1/4 of the FIFO is probably a good number) your design should start outputting audio samples to the DAC. This should be done at a rate of 2KHz until the FIFO is emptied.DetailsThe audio transmission half of the design is pretty straightforward. When there is data in the FIFO and the packet-logic is not preoccupied with a previous packet, then start the construction of a new packet. Then transmit the packet when the network is available. The audio reception part however has a few subtleties:a) You don’t want to start sending data to the DAC as soon as there are samples in the FIFO. This is because again the behavior of a shared network in a short amount of time can vary. Therefore you could end up having to drop samples because the next packet did not arrive in time. This is why you must fill up the FIFO to a certain degree before you start outputting samples to the DAC.b) Even with buffering in the FIFO you could still run into buffer under or overflow if the transmission is long enough. This is because the 16MHz oscillator on each board are not identical therefore there must be some frequency difference. And since your 2KHz sampling/output rate is derived from the oscillator you are bound to output either slower or faster than you are receiving. This is where the buffer will help, as long as the transmission is not too long your output will not need to drop samples. c) The way your design should work is, fill up the FIFO to say ¼ full before you start outputting to the DAC. Once you start outputting to the DAC keep on outputting at a 2KHz interval, do not stop till the FIFO is empty. Once the FIFO is empty then repeat the process of fill up again. In the unlikely event that the FIFO overflows you are allowed to drop the extra samples.d) So far we have been assuming that there is only one transmission directed at your board. This doesn’t always have to be true. Your design should gracefully handle 2 audio streams both directed at the same station. In this situation it is not okay to just dump both streams into the FIFO, by doing that you are interleaving audio samples, this will produce output audio that is garbage as well as overflow the FIFO. The cleaver thing to do is to recognize multiple incoming streams and mix the audio; however that is hard to do as it will probably require multiple head pointers for the FIFO or other cleaver tricks. For the final project you are required to do something simpler. If there are multiple input audio streams you simply ignore all but one of them. This requires your design to remember the source of the transmission that is currently in the FIFO.e) Since you are waiting to fill up the FIFO to ¼ capacity before you start sending to the DAC there is the problem of if the entire audio transmission does not fill the FIFO to ¼ capacity then you will never start transmission. To solve this problem you will need to add a counter that makes sure that you start outputting to the DAC after a certain amount of time even if the FIFO is not fill to ¼. I’ll leave it to you to figure out how long the counter should count and when it should start.User Interface DescriptionDipswitches.From checkpoint 4, your entire header byte came from the dipswitches. Since the 2 control bits don’t really have to come from the dipswitches, those 2 dipswitches will be used for setting the mode in thefinal project. The entire basic project as described so far is mode 00. (i.e. both bits set to 0) This is the only mandatory mode. In mode 00 all packets are transmitted with 00 in the control bit of the header byte. For some extra credit you may
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