EECS 150 - Components and Design Techniques for Digital SystemsLec 16 – Arithmetic II (Multiplication)David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs150Overview• Review of Addition• Overflow• Multiplication• Further adder optimizations for multiplication• CLA in the large – parallel prefixReview• Circuit design for unsigned addition– Full adder per bit slice– Delay limited by Carry Propagation» Ripple is algorithmically slow, but wires are short• Carry select– Simple, resource-intensive– Excellent layout• Carry look-ahead– Excellent asymptotic behavior– Great at the board level, but wire length effects are significant on chip• Digital number systems– How to represent negative numbers– Simple operations– Clean algorithmic properties• 2s complement is most widely used– Circuit for unsigned arithmetic– Subtract by complement and carry in– Overflow when cin xor cout of sign-bit is 1Computer Number Systems• Positional notation– Dn-1Dn-2…D0represents Dn-1Bn-1+ Dn-2Bn-2+ …+ D0B0 where Di∈ { 0, …, B-1 }• 2s Complement– Dn-1Dn-2…D0represents: -Dn-12n-1+ Dn-22n-2+ …+ D020– MSB has negative weight0000000100100011100001010110010010011010101111001101011111101111+0+1+2+3+4+5+6+7-8-7-6-5-4-3-2-1-8 + 52s Complement OverflowAdd two positive numbers to get a negative numberor two negative numbers to get a positive number5 + 3 = -8!-7 - 2 = +7!0000000100100011100001010110010010011010101111001101011111101111+0+1+2+3+4+5+6+7-8-7-6-5-4-3-2-10000000100100011100001010110010010011010101111001101011111101111+0+1+2+3+4+5+6+7-8-7-6-5-4-3-2-1How can you tell an overflow occurred?2s comp. Overflow Detection53-80 1 1 10 1 0 10 0 1 11 0 0 0-7-271 0 0 01 0 0 11 1 0 01 0 1 1 15270 0 0 00 1 0 10 0 1 00 1 1 1-3-5-81 1 1 11 1 0 11 0 1 11 1 0 0 0OverflowOverflowNo overflowNo overflowOverflow occurs when carry in to sign does not equal carry out2s Complement Adder/SubtractorA - B = A + (-B) = A + B + 1A B CO S + CI A B CO S + CI A B CO S + CI A B CO S + CI 0 1 Add/Subtract A 3 B 3 B 3 0 1 A 2 B 2 B 2 0 1 A 1 B 1 B 1 0 1 A 0 B 0 B 0 Sel Sel Sel Sel S 3 S 2 S 1 S 0 Overflow Adders on the Xilinx Virtex• Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB.• The arithmetic logic includes an XOR gate and AND gate that allows a 2-bit full adder to be implemented within a slice. • Cin to Cout delay = 0.1ns, versus 0.4ns for F to X delay.How do we map a 2-bit adder to one slice?Time / Space (resource) Trade-offs• Carry select and CLA utilize more silicon to reduce time.• Can we use more time to reduce silicon?• How few FAs does it take to do addition?Bit-serial Adder• Addition of 2 n-bit numbers:– takes n clock cycles,– uses 1 FF, 1 FA cell, plus registers– the bit streams may come from or go to other circuits, thereforethe registers may be optional.• Requires controller– What does the FSM look like? Implemented?• Final carry out?• A, B, and R held in shift-registers. Shift right once per clock cycle.• Reset is asserted by controller.n-bit shift registern-bit shift registersscresetRFAFFBAlsbDiscussion• What is sign extension and why does it work?• Where is addition used in the project?• Where might you want more powerful arithmetic operations?Announcements• Reading: 5.8 (4 pages!)• Digital Design in the news – from UCB– UC Berkeley is among six universities to be part of the program started by IBM Corp. and Google Inc. on college campuses to promote computer-programming techniques for clusters of processors known as "clouds". Cloud computing allows computers in remote data centers to run parallel, increasing their processing power. Each company will spend between $20 million and $25 million for hardware, software and services that can be used by computer-science professors and students.Basic concept of multiplicationmultiplicandmultiplier1101 (13)1011 (11)1101110100001101*10001111(143)Partial products• product of 2 n-bit numbers is an 2n-bit number– sum of n n-bit partial products• unsignedCombinational Multiplier:accumulation of partial productsA0B0A0 B0A1B1A1 B0A0 B1A2B2A2 B0A1 B1A0 B2A3B3A2 B0A2 B1A1 B2A0 B3A3 B1A2 B2A1 B3A3 B2A2 B3A3 B3S6S5S4S3 S2S1 S0S7Array Multiplierb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a10a20a30P0P1P2P3FAbjsum insum outcarryoutaicarryinEach row: n-bit adder with AND gatesWhat is the critical path?Generates all n partial products simultaneously.“Shift and Add” Multiplier• Sums each partial product, one at a time.• In binary, each partial product is shifted versions of A or 0.Control Algorithm:1. P ← 0, A ← multiplicand, B ← multiplier2. If LSB of B==1 then add A to Pelse add 03. Shift [P][B] right 14. Repeat steps 2 and 3 n-1 times.5. [P][B] has product.Bn-bit shift registersPAn-bit register+010 n-bit adder• Cost α n, Τ = n clock cycles.• What is the critical path for determining the min clock period?Carry-save Addition• Speeding up multiplication is a matter of speeding up the summing of the partial products.• “Carry-save” addition can help.• Carry-save addition passes (saves) the carries to the output, rather than propagating them.• Example: sum three numbers,310= 0011, 210= 0010, 310= 00113100011+ 2100010c 0100 = 410s 0001 = 1103100011c 0010 = 210s 0110 = 6101000 = 810carry-save addcarry-save addcarry-propagate add• In general, carry-save addition takes in 3 numbers and produces 2.• Whereas, carry-propagate takes 2 and produces 1.• With this technique, we can avoid carry propagation until final additionCarry-save Circuits• When adding sets of numbers, carry-save can be used on all but the final sum.• Standard adder (carry propagate) is used for final sum.FAFAFA FAFA FA FA FA0CSAs cs cs cs cs cs cs cs ccCSACPACSACSAx0x1x2Array Mult. using Carry-save Additionb3 0 b2 0 b1 0 b0 0P7 P6 P5 P4a00a1a2a3P0P1P2P310000000000FAbjsum insum outcarryoutaicarryinFast carry-propagate adderAnother RepresentationA3 B0SCA2 B0SCA1 B0SCA0 B0SCA3 B1SCA2 B1SCA1 B1SCA0 B1SCA3 B2SCA2 B2SCA1 B2SCA0 B2SCA3 B3SCA2 B3SA1 B3SA0 B3SB0B1B2B3P7 P6 P5 P4 P3 P2 P1 P0A3 A2A1A0Building
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