University of California at BerkeleyCollege of EngineeringEECS150 J. WawrzynekSpring 2000 E. CaspiLab #10: Audio Output (DAC+Amp)1 Objectives2 Digital-to-Analog Converter (DAC)3 Audio Amplifier4 Lab Assignment5 Acknowledgements6 Check-offs (Lab #10: Audio Output)Pre-labLab AssignmentMIDI Lab AddendumUniversity of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS150 J. WawrzynekSpring 2000 E. CaspiLab #10: Audio Output (DAC+Amp)This is the final lab involving installation of hardware on the Xilinx boards. It is to be completed with a project partner on your assigned project board. Following this lab, the remainder of the project will consist of programming your board.1 ObjectivesThe primary objectives of this lab are:- Learn how to interface to a Digital-to-Analog Converter (DAC)- Equip your project board with a complete audio output stageThe hardware side of this lab involves wire-wrapping a digital-to-analog converter (DAC) and audio amplifier to your Xilinx board, along with several discretes (resistors, capacitors). The software side of this lab involves writing a serial interface to the DAC and a simple waveform generator with which to test the DAC interface.2 Digital-to-Analog Converter (DAC)A DAC is a device that converts a sequence of numbers into an analog waveform. Our synthesizer needs a DAC to convert sound samples into an electric signal which, with proper amplification, can drive a loudspeaker or headphones.We will use the Analog Devices AD1866 dual 16-bit audio DAC. A datasheet and wire-wrap ID guide will be available on the course web-page. This particular DAC supports two audio channels, but we will use only the left channel (L). The DAC converts 16-bit, two’s-complement words into output voltage levels. Each word must be shifted into the DAC serially (via pin DL, “Data Left”), MSB first, in-sync with a clock signal (CLK). Once an entire word is shifted in, the falling edge of a control signal (LL, “Latch Left”) instructs the DAC to convert that word into a voltage. We will send 16-bit samples to the DAC at a sample rate matching the MIDI baud rate, namely 31.25kHz. The bits of each sample will be serially shifted into the DAC at a rate of 8MHz.3 Audio AmplifierThe DAC’s analog output is too weak to drive a loudspeaker or headphones on its own. Itmust be passed through an amplifier that can supply enough current and power to make audible sound.We will use the National Semiconductor LM4862 Boomer 675mW audio power amplifier.A datasheet and wire-wrap ID guide will be available on the course web page. One interesting feature of this IC is that it can be turned off by driving one of its input pins (SHUTDOWN) high. We will drive that pin from the FPGA to control when the amplifier turns on. Your design should drive the SHUTDOWN pin low to keep the amp on. The Xilinx I/O pins default to logic-high when the FPGA is powered-on, providing a mechanism to keep the amplifier off until it is configured with your design.The amplifier’s differential outputs (Vo1, Vo2) should be connected to the 1/8-inch phones connector on the Xilinx board. Our phones connector has 3 conductors (tip, ring, sleeve) to support stereo sound. The tip and ring, which represent the left and right audio channels, should be tied together using wire-wrap. Connect one amp output to the tip-ring pair and the other amp output to the sleeve. 4 Lab AssignmentFor the hardware part of this lab, you must wire-wrap the DAC, amplifier, and discretes toyour project board. There are two discrete packs, one per IC. Try to place the ICs (DAC and amp) close to the periphery of the wire-wrap area, where they can be close to a power/ground pin pair (labeled “- +” on the board). Straddling each such pin pair is a 1/8-inch phones connector + hookup to amplifierSleeveRingTipVo1Vo20.1-F bypass capacitor that can provide a small burst of current to an IC’s power/ground pins. This capacitor helps keep an IC’s supply voltage constant as its power draw fluctuates. If an IC is not close to the board periphery, connect a bypass capacitor from one of the discrete packs between the IC’s power and ground pins. Bypass capacitors should always be as close as possible to an IC (ideally, soldered on), since the inductance of wire connections diminishes their effectiveness.The DAC and amplifier can be connected to the FPGA’s unused pins 6-9. For standardization, please use the pins in the following table. We suggest that the 8MHz clock also be connected to pin 37 or 41 in order to flash a decimal LED while the circuit is active.Signal FPGA PinDAC LD 6DAC LL 7Amp SHUTDOWN 8DAC CLK (8MHz) 9, (37 or 41)Pin connections for DAC and amplifierA wiring schematic for the DAC and amplifier is attached. All resistors and capacitors in the schematic are soldered to the discrete packs. They must be connected as shown in order for the ICs to function properly.For the software part of this lab, you must construct two circuit designs:1. A parallel-to-serial converter to drive the DAC’s LD and LL inputs.This may be done in a variety ways, typically using a shift register and some additional logic. Keep in mind that a new 16-bit sample must be fed to the DAC every 32-s so as to match the sample rate with the MIDI baud rate of 31.25kHz. Thus LL should send a down-edge once every 32-s, immediately following a 16-bit serial transmission to LD at 8MHz. Consult the DAC data sheet for precise timing information. Mistiming the LL down edge will result in failure to shift-in the sample’s LSB, or alternatively, will shift-in a superfluous LSB. The result may be benign (e.g. 2- error in amplitude) or quite drastic (e.g. noise due to spurious changes in sign of samples – remember, the sample MSB is a sign bit).2. A sawtooth wave generator to test the DAC interface.This circuit produces a sawtooth (ramp) wave of audible frequency, represented by31250 16-bit samples per second. You may choose your own frequency. Forexample, a frequency of 1000Hz can be generated by counting from 0 to 31 on a 31.25kHz clock (strictly speaking, count –16 to 15, since the DAC expects two’s-complement samples). Full-amplitude 16-bit samples can be generated by placingthis 5-bit count in the most significant bits and concatenating 11 trailing zeros.For pre-lab, create schematics for the DAC interface and waveform generator. Test your circuits in
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