1128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.128Mb: x4, x8, x16SDRAMPRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.32 Meg x 4 16 Meg x 8 8 Meg x 16Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banksRefresh Count 4K 4K 4KRow Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)SYNCHRONOUSDRAMMT48LC32M4A2 – 8 Meg x 4 x 4 banksMT48LC16M8A2 – 4 Meg x 8 x 4 banksMT48LC8M16A2 – 2 Meg x 16 x 4 banksFor the latest data sheet, please refer to the Micron Website: www.micron.com/dramdsPIN ASSIGNMENT (Top View)54-Pin TSOPFEATURES• PC100-, and PC133-compliant• Fully synchronous; all signals registered on positiveedge of system clock• Internal pipelined operation; column address can bechanged every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths: 1, 2, 4, 8, or full page• Auto Precharge, includes CONCURRENT AUTOPRECHARGE, and Auto Refresh Modes• Self Refresh Mode; standard and low power• 64ms, 4,096-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V ±0.3V power supplyOPTIONS MARKING• Configurations32 Meg x 4 (8 Meg x 4 x 4 banks) 32M416 Meg x 8 (4 Meg x 8 x 4 banks) 16M88 Meg x 16 (2 Meg x 16 x 4 banks) 8M16• WRITE Recovery (tWR)tWR = “2 CLK”1A2• Package/PinoutPlastic Package – OCPL254-pin TSOP II (400 mil) TG60-ball FBGA (8mm x 16mm) FB 3,660-ball FBGA (11mm x 13mm) FC 3,6• Timing (Cycle Time)10ns @ CL = 2 (PC100) -8E 3,4,57.5ns @ CL = 3 (PC133) -757.5ns @ CL = 2 (PC133) -7E• Self RefreshStandard NoneLow power L• Operating Temperature RangeCommercial (0oC to +70oC) NoneIndustrial (-40oC to +85oC) IT 3Part Number Example:MT48LC16M8A2TG-7ENOTE: 1. Refer to Micron Technical Note: TN-48-05.2. Off-center parting line.3. Consult Micron for availability.4. Not recommended for new designs.5. Shown for PC100 compatability.6. See page 59 for FBGA Device Marking Table.VDDDQ0VDDQDQ1DQ2VssQDQ3DQ4VDDQDQ5DQ6VssQDQ7VDDDQMLWE#CAS#RAS#CS#BA0BA1A10A0A1A2A3VDD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VssDQ15VssQDQ14DQ13VDDQDQ12DQ11VssQDQ10DQ9VDDQDQ8VssNCDQMHCLKCKENCA11A9A8A7A6A5A4Vssx8x16 x16x8 x4x4-DQ0-NCDQ1-NCDQ2-NCDQ3-NC-NC-------------NC-NCDQ0-NCNC-NCDQ1-NC-NC-------------DQ7-NCDQ6-NCDQ5-NCDQ4-NC--DQM------------NC-NCDQ3-NCNC-NCDQ2 -NC--DQM-----------Note: The # symbol indicates signal is active LOW. A dash (–)indicates x8 and x4 pin function is same as x16 pin function.KEY TIMING PARAMETERSSPEED CLOCK ACCESS TIME SETUP HOLDGRADE FREQUENCY CL = 2* CL = 3* TIME TIME-7E 143 MHz – 5.4ns 1.5ns 0.8ns-7E 133 MHz 5.4ns – 1.5ns 0.8ns-75 133 MHz – 5.4ns 1.5ns 0.8ns-8E 3,4,5125 MHz – 6ns 2ns 1ns-75 100 MHz 6ns – 1.5ns 0.8ns-8E 3 ,4,5100 MHz 6ns – 2ns 1ns*CL = CAS (READ) latency2128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.128Mb: x4, x8, x16SDRAMFBGA BALL ASSIGNMENT(Top View)ABCDEFGHJKLMNPR12345678Depopulated BallsNCVssNCVssQVDDQDQ3NCNCNCVssQVDDQDQ2NCNCNCVssNCDQMNCCKNCCKEA11A9A8A7A6A5A4VssVDDNCVDDQNCDQ0VssQNCNCVDDQNCDQ1VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA332 Meg x 48 x 16mm and 11 x 13mmABCDEFGHJKLMNPR12345678Depopulated BallsDQ7VssNCVssQVDDQDQ6DQ5NCNCVssQVDDQDQ4NCNCNCVssNCDQMNCCKNCCKEA11A9A8A7A6A5A4VssVDDDQ0VDDQNCDQ1VssQNCDQ2VDDQNCDQ3VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA316 Meg x 88 x 16mm and 11 x 13mm3128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.128Mb: x4, x8, x16SDRAMA0-A11 select the row). The address bits registeredcoincident with the READ or WRITE command are usedto select the starting column location for the burstaccess.The SDRAM provides for programmable READor WRITE burst lengths of 1, 2, 4, or 8 locations, or thefull page, with a burst terminate option. An autoprecharge function may be enabled to provide a self-timed row precharge that is initiated at the end of theburst sequence.The 128Mb SDRAM uses an internal pipelinedarchitecture to achieve high-speed operation. Thisarchitecture is compatible with the 2n rule of prefetcharchitectures, but it also allows the column address to bechanged on every clock cycle to achieve a high-speed,fully random access. Precharging one bank while access-ing one of the other three banks will hide the prechargecycles and provide seamless high-speed, random-accessoperation.The 128Mb SDRAM is designed to operate in 3.3Vmemory systems. An auto refresh mode is provided, alongwith a power-saving, power-down mode. All inputs andoutputs are LVTTL-compatible.SDRAMs offer substantial advances in DRAM operat-ing performance, including the ability to synchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between in-ternal banks in order to hide precharge time and thecapability to randomly change column addresses on eachclock cycle during a burst access.GENERAL DESCRIPTIONThe Micron® 128Mb SDRAM is a high-speed CMOS,dynamic random-access memory containing 134,217,728bits. It is internally configured as a quad-bank DRAMwith a synchronous interface (all signals are registered onthe positive edge of the clock signal, CLK). Each of the x4’s33,554,432-bit banks is organized as 4,096 rows by 2,048columns by 4 bits. Each of the x8’s 33,554,432-bit banks isorganized as 4,096 rows by 1,024 columns by 8 bits. Eachof the x16’s 33,554,432-bit banks is organized as 4,096rows by 512 columns by 16 bits.Read and write accesses to the SDRAM are burst ori-ented; accesses start at a selected location and continuefor a programmed number of locations in a programmedsequence. Accesses begin with the registration of an AC-TIVE command, which is then followed by a READ orWRITE command. The address bits registered coinci-dent with the ACTIVE command are used to select thebank and row to be accessed (BA0, BA1 select the bank;PART NUMBER ARCHITECTUREMT48LC32M4A2TG 32 Meg x 4MT48LC32M4A2FC* 32 Meg x 4MT48LC32M4A2FB* 32 Meg x
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