1EECS 150 Spring 2003Lab Lecture 10Final Project I4/10/2003Sandro Pintz Asynchronous Clock Crossings The world is Asynchronous 100% chance to encounter issues No Exhaustive Simulation Possible Failures could be very sporadic and environmentally dependant Failures are very hard to debug2Most Common Cases External Signals Coming into Synchronous Designs Interfacing to external standard interfaces: PCI (33/66 MHz) Video (27 MHz) Networking (100 MHz) System Optimization (Area/Performance/Heat Dissipation)What is the problem? Will be covered by JohnW in class, but … to give you an idea From fast to slow clock: Miss a pulse From slow to fast clock: double pulse Metastability if we violate setup or hold time on synchronous elements Result: Malfunction!3Level Synchronization Input is stable for a long time Output is stable for a long time Delay of at most 3 clocks… why?QQSETCLRDQQSETCLRDReceiving ClockSynchronizedLevelAsynchronousLevelPulse Synchronization (1) From Slow Clock to Fast Clock Source pulse could be captured twiceOutput PulseQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDFast ReceivingClockSlow SourceClockSource Pulse4Pulse Synchronization (2)QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDPulse InSource Clk Receiving Clock From Fast Clock to Slow Clock or From Slow Clock to Fast ClockPulse Synchronization (3) In Source region we don’t know when pulse happened in Receiving RegionClk2SynchDataClk1write enableWhen is it written here? ..Can we overwrite here?5Pulse Synchronization (4)QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDPulse InPulse OutSource Clk Receiving ClockAcknowledge We need Full HandshakeGlitches Combination logic generates glitches because of different prop. delays. A unintended glitch can easily be captured by another clock Use only glitch-free signals to go across clock domains!!! How do you guarantee glitch-free?6Races You can’t assume the arrival time of two simultaneous signals that go across clock domains!Clk2SynchClk1Synchin1in2out1out2If they show up at the sametime here ....it doesn't mean ...they will show up at thesame time here .....Data, Fifos (1) Do NOT Synchronize whole data busses Race conditions! Synchronize only the control signals for it If you need to balance data rates across domains -> Use Asynchronous FIFOs7Data, Fifos (2)Register Fileor Dual PortMemoryWrite Pointer(counter)Read Pointer(counter)FullLogicEmptyLogicread enableread clockData InData OutSynch.LogicSynch.LogicData, Fifos (3) Use gray counters to synchronize pointers: Change 1-bit for every count => no race conditions! There is a delay from write enable to fifo full There is a delay from read enable to fifo
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