University of California, BerkeleyCS150 Final ReportVideo Conferencing SystemBy Team Dumassmans4/25/20072Table of ContentsThe Big Picture...............................................................................................................................4Motivation.......................................................................................................................................4Abstract..........................................................................................................................................4Layout ............................................................................................................................................4Checkpoint 0 - SDRAM Controller.............................................................................................. 5Objective ........................................................................................................................................5Design Methodology ........................................................................................................................532-bits using 16-bit RAM...............................................................................................................5SDRAM Timing.............................................................................................................................5SDRAM Properties ........................................................................................................................5State Machine Design...................................................................................................................5Design Tradeoffs .............................................................................................................................5Checkpoint 1 – Video Encoder..................................................................................................6Objective ........................................................................................................................................6Design Methodology ........................................................................................................................6Row and Column Counters............................................................................................................6InRequest Signals ........................................................................................................................6EAV and SAV signals.....................................................................................................................6Output Selection ..........................................................................................................................6State Machine Design...................................................................................................................6Design Tradeoffs .............................................................................................................................6Diagrams ........................................................................................................................................7Block Diagram..............................................................................................................................7Checkpoint 2 – Local Video: ...................................................................................................... 8Objective ........................................................................................................................................8Design Methodology ........................................................................................................................8SDRAM Arbiter.............................................................................................................................8Video Decoder RAM Processor.......................................................................................................8Video Encoder RAM Processor.......................................................................................................8Text Overlay................................................................................................................................8State Machine Design...................................................................................................................9Design Tradeoffs .............................................................................................................................9Diagrams ........................................................................................................................................9Arbiter.........................................................................................................................................93Checkpoint 3 – Wireless Transceiver........................................................................................10Objective ......................................................................................................................................10Design Methodology ......................................................................................................................10General Design Patterns .............................................................................................................10The Serial Parallel Interface (SPI Module)....................................................................................10Handshaking..............................................................................................................................10State Machine Design.................................................................................................................10Design Tradeoffs ...........................................................................................................................10Diagrams ......................................................................................................................................11Overall Transceiver.....................................................................................................................11Receiver
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