EECS 150 - Components and Design Techniques for Digital Systems Lec 14 – Storage: DRAM, SDRAMRecall: Basic Memory Subsystem Block DiagramQuestionProblems with SRAM1-Transistor Memory Cell (DRAM)Classical DRAM Organization (Square)DRAM Logical Organization (4 Mbit)ExamplesLogic Diagram of a Typical DRAMBasic DRAM read & writeDRAM READ TimingEarly Read SequencingSketch of Early Read FSMLate Read SequencingSketch of Late Read FSMAdmin / AnnouncementsDRAM WRITE TimingKey DRAM Timing ParametersMemory in Desktop Computer Systems:DRAM with Column bufferOptimized Access to Cols in RowMore recent DRAM enhancementsSlide 23SDRAM DetailsREAD burst (with auto precharge)WRITE burst (with auto precharge)Volatile Memory ComparisonSDRAM Recap10/11/2007EECS150 Fa07 - DRAM1EECS 150 - Components and Design Techniques for Digital Systems Lec 14 – Storage: DRAM, SDRAM David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs15010/11/2007EECS150 Fa07 - DRAM2Recall: Basic Memory Subsystem Block DiagramAddressDecoderWord Linen AddressBits2n wordlinesm Bit LinesMemorycellwhat happensif n and/or m isvery large?RAM/ROM naming convention: 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words10/11/2007EECS150 Fa07 - DRAM3Question•What is the difference between a clock signal and a strobe?10/11/2007EECS150 Fa07 - DRAM4Problems with SRAM•Six transistors use up lots of area•Consider a “Zero” is stored in the cell:–Transistor N1 will try to pull “bit” to 0–Transistor P2 will try to pull “bit bar” to 1•If Bit lines are pre-charged high: are P1 and P2 really necessary?–Read starts by precharging bit and ~bit–Selected cell pulls one of them low–Sense the differencebit = 1 bit = 0Select = 1On OfOf OnN1 N2P1 P2OnOn10/11/2007EECS150 Fa07 - DRAM51-Transistor Memory Cell (DRAM)•Write:–1. Drive bit line–2. Select row•Read:–1. Precharge bit line to Vdd/2–2. Select row–3. Cell and bit line share charges»Minute voltage changes on the bit line–4. Sense (fancy sense amp)»Can detect changes of ~1 million electrons–5. Write: restore the value •Refresh–1. Just do a dummy read to every cell. (row)row selectbitRead is really aread followed bya restoring write10/11/2007EECS150 Fa07 - DRAM6Classical DRAM Organization (Square)rowdecoderrowaddressColumn Selector & I/O CircuitsColumnAddressdataRAM Cell Arrayword (row) selectbit (data) linesRow and Column Address together select 1 bit a timeEach intersection representsa 1-T DRAM CellSquare keeps the wires short:Power and speed advantagesLess RC, faster precharge anddischarge is faster access time!10/11/2007EECS150 Fa07 - DRAM7DRAM Logical Organization (4 Mbit)•Square root of bits per RAS/CAS–Row selects 1 row of 2048 bits from 2048 rows–Col selects 1 bit out of 2048 bits in such a rowColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage CellROWDECODER114 Mbit = 22 address bits 11 row address bits 11 col address bits10/11/2007EECS150 Fa07 - DRAM8ExamplesIBM 4 Mb DRAM (Dynamic Random Access Memory) chip introduced in 1989. Shown against acorn and fall foliage leaves in Burlington, Vermont where it was manufactured. IBM 16 Mb EC/Memeory ChipIBM 512M SDRAM Chip10/11/2007EECS150 Fa07 - DRAM9ADOE_L256K x 8DRAM9 8WE_L•Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low•Din and Dout are combined (D):–WE_L is asserted (Low), OE_L is disasserted (High)»D serves as the data input pin–WE_L is disasserted (High), OE_L is asserted (Low)»D is the data output pin•Row and column addresses share the same pins (A)–RAS_L goes low: Pins A are latched in as row address–CAS_L goes low: Pins A are latched in as column address–RAS/CAS edge-sensitiveCAS_LRAS_LLogic Diagram of a Typical DRAM10/11/2007EECS150 Fa07 - DRAM10Basic DRAM read & write•Strobe address in two steps10/11/2007EECS150 Fa07 - DRAM11ADOE_L256K x 8DRAM9 8WE_LCAS_LRAS_LOE_LA Row AddressWE_LJunkRead AccessTimeOutput EnableDelayCAS_LRAS_LCol Address Row Address JunkCol AddressD High Z Data OutDRAM Read Cycle TimeEarly Read Cycle: OE_L asserted before CAS_LLate Read Cycle: OE_L asserted after CAS_L•Every DRAM access begins at:–Assertion of the RAS_L–2 ways to read: early or late v. CAS Junk Data Out High ZDRAM READ Timing10/11/2007EECS150 Fa07 - DRAM12Early Read Sequencing•Assert Row Address•Assert RAS_L–Commence read cycle–Meet Row Addr setup time before RAS/hold time after RAS•Assert OE_L•Assert Col Address•Assert CAS_L–Meet Col Addr setup time before CAS/hold time after CAS•Valid Data Out after access time•Disassert OE_L, CAS_L, RAS_L to end cycle10/11/2007EECS150 Fa07 - DRAM13Sketch of Early Read FSMRow Address to MemoryAssert RAS_LSetup time met?FSM Clock?Assert OE_L, RAS_LCol Address to MemoryHold time met?Assert OE_L, RAS_L, CAS_LSetup time met?Hold time met?Assert OE_L, RAS_L, CAS_LData Available (better grab it!)10/11/2007EECS150 Fa07 - DRAM14Late Read Sequencing•Assert Row Address•Assert RAS_L–Commence read cycle–Meet Row Addr setup time before RAS/hold time after RAS•Assert Col Address•Assert CAS_L–Meet Col Addr setup time before CAS/hold time after CAS•Assert OE_L•Valid Data Out after access time•Disassert OE_L, CAS_L, RAS_L to end cycle10/11/2007EECS150 Fa07 - DRAM15Sketch of Late Read FSMRow Address to MemoryAssert RAS_LSetup time met?FSM Clock?Col Address to MemoryAssert RAS_LHold time met?Col Address to MemoryAssert RAS_L, CAS_LSetup time met?Hold time met?Assert OE_L, RAS_L, CAS_LData Available (better grab it!)10/11/2007EECS150 Fa07 - DRAM16Admin / Announcements•Usual homework story•Read: 10.4.2-3 and SDRAM data sheet•We have time to understand memory protocols before using them.•Proposal for a “low impact Mid III”–1 problem a day in class over 4-5 classes.10/11/2007EECS150 Fa07 - DRAM17ADOE_L256K x 8DRAM9 8WE_LCAS_LRAS_LWE_LA Row AddressOE_LJunkWR Access Time WR Access TimeCAS_LRAS_LCol Address Row Address JunkCol AddressD Junk JunkData In Data In JunkDRAM WR Cycle TimeEarly Wr Cycle: WE_L asserted before CAS_L Late Wr Cycle: WE_L asserted after CAS_L•Every DRAM access begins at:–The assertion of the RAS_L–2 ways to write: early or late v. CASDRAM WRITE Timing10/11/2007EECS150 Fa07 - DRAM18Key DRAM Timing Parameters•tRAC: minimum time from RAS line falling to the valid data output. –Quoted as the speed of a
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