EECS 150 - Components and Design Techniques for Digital Systems Lec 26 - WrapUpAnnouncementsRecall: Day 1CongratulationsDay 1: What is EECS150 about?Day 1: We Will Learn in EECS 150 …Day 26: Ready to tackle ANY digital designTackling complex digital designsFor ExampleTraversing Digital DesignIn Each: Datapath and ControlSlide 12What makes Digital Systems tick?Register Transfer Level DescriptionsA Register TransferRegister Transfers - interconnectData Path (Bit-slice)Approaching an ISAInstruction TypesHardware Necessary To Implement InstructionsFSM Controller for CPURepresenting Numbers2s Complement OverflowComputer Arithmetic2s Complement Adder/SubtractorCombinational Multiplier: accumulation of partial productsAnother RepresentationDigital Number SystemsCircuits for Fixed-Point ArithmeticLet’s build an FP function unit: multWhat is the range of mantissas?Cascaded Carry LookaheadParallel Prefix (generalizing CLA)Basic Memory Subsystem Block DiagramTypical SRAM TimingDRAM WRITE TimingDRAM with Column bufferHamming Error Correcting CodeExample: 8 bit SECExample: Ethernet CRC-32General Model of Synchronous CircuitGate Switching BehaviorXilinx Virtex-E FloorplanLimitations on Clock RateTiming MethodologiesMaster-Slave StructureSlide 48(neg) Edge-Triggered Flip-FlopsTwo-phase non-overlapping clocksSlide 51Slide 52Review: Two Kinds of FSMsReview: Finite State Machine RepresentationsReview: Formal Design ProcessMoore Verilog FSM: combinational partMoore Verilog FSM: state partFSM OptimizationAlgorithmic Approach to State MinimizationMinimized FSMState Assignment StrategiesSlide 62Design ProcessSlide 64TestingFault ModelReally putting it togetherSlide 68Controlling Energy Consumption: What Control Do You Have as a Designer?Day 1: CS 150: Concepts/Skills/AbilitiesBroad Technology TrendsGo Forth and Design!EECS 150 - Components and Design Techniques for Digital Systems Lec 26 - WrapUp David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs150http://www.youtube.com/watch?v=Tb2Q1GGEYA401/14/19EECS 150, Fa07, Lec 26 - wrap2Announcements•Final Exam–TUESDAY, DECEMBER 18, 2007 5-8P–Location: 106 STANLEY–Course Control Number: 26455–Final Exam Group: 15•TA office hours tues AM•Review Sunday 12/16 5-7 @ 125 Cory•Project Partner forms into HW box•Project Presentations Friday as per SignUp•No lecture thurs, no labs, no discussion•Office Hours•HW 10 in box wed01/14/19EECS 150, Fa07, Lec 26 - wrap3Recall: Day 18/28/07EECS150 F07 Lec01 - Intro5© UC BerkeleyDigital Design in Your Life…Your ideas here …01/14/19EECS 150, Fa07, Lec 26 - wrap4Congratulations•You have accomplished a phenomenal task.DisplayInternalsHand input (limited)AudioCamera (optional)Wireless Networki50talki50choosenotifications01/14/19EECS 150, Fa07, Lec 26 - wrap5Day 1: What is EECS150 about?Transfer FunctionTransistor PhysicsDevicesGatesCircuitsFlipFlopsEE 40HDLMachine OrganizationInstruction Set ArchPgm Language Asm / Machine LangCS 61CDeep Digital Design ExperienceFundamentals of Boolean LogicSynchronous CircuitsFinite State MachinesTiming & ClockingDevice Technology & ImplicationsController DesignArithmetic UnitsBus DesignEncoding, FramingTesting, DebuggingHardware ArchitectureHDL, Design Flow (CAD)01/14/19EECS 150, Fa07, Lec 26 - wrap6Day 1: We Will Learn in EECS 150 …•Language of logic design–Logic optimization, state, timing, CAD tools•Concept of state in digital systems–Analogous to variables and program counters in software systems•Hardware system building–Datapath + control = digital systems•Hardware system design methodology–Hardware description languages: Verilog–Tools to simulate design behavior: output = function (inputs)–Logic compilers synthesize hardware blocks of our designs–Mapping onto programmable hardware (code generation)•Contrast with software design–Both map specifications to physical devices–Both must be flawless …01/14/19EECS 150, Fa07, Lec 26 - wrap7Day 26: Ready to tackle ANY digital design01/14/19EECS 150, Fa07, Lec 26 - wrap8Tackling complex digital designs•Step 1: Decompose the system into a collection of subsystems–Each has top-down requirements and bottom-up constraints–Interconnected through interfaces–Often with particular protocols–Potentially different clock domains–Rate matching, buffering, timing•For example…01/14/19EECS 150, Fa07, Lec 26 - wrap9For Example•Encodings•Protocols•Synchronization•Commands•Formats•Specifications•DatasheetsDisplayHand input (limited)AudioCamera (optional)NetworkCC2420 Clock domainADV7194 Clock DomainVideo encoderAC97 Clock domain01/14/19EECS 150, Fa07, Lec 26 - wrap10Traversing Digital Design EE 40CS61CEECS150 wks 1-6EECS150 wks 6-1501/14/19EECS 150, Fa07, Lec 26 - wrap11In Each: Datapath and Control•Datapath: Storage, FU, interconnect sufficient to perform the desired functions–Inputs are Control Points–Outputs are signals•Controller: State machine to orchestrate operation on the data path–Based on desired function and signalsDatapathControllerControl Pointssignals01/14/19EECS 150, Fa07, Lec 26 - wrap12Tackling complex digital designs•Step 1: Decompose the system into a collection of subsystems–Each has top-down requirements and bottom-up constraints–Interconnected through interfaces–Often with particular protocols–Potentially different clock domains–Rate matching, buffering, timing•For Each Subsystem•Step2: Design the Datapath01/14/19EECS 150, Fa07, Lec 26 - wrap13What makes Digital Systems tick?CombinationalLogictimeclk01/14/19EECS 150, Fa07, Lec 26 - wrap14Register Transfer Level Descriptions•A standard high-level representation for describing systems.•It follows from the fact that all synchronous digital system can be described as a set of state elements connected by combination logic (CL) blocks:•RTL comprises a set of register transfers with optional operators as part of the transfer.•Example:regA regBregC regA + regBif (start==1) regA regC•Personal style:–use “;” to separate transfers that occur on separate cycles.–Use “,” to separate transfers that occur on the same cycle.•Example (2 cycles):regA regB, regB 0;regC regA;r e g r e gC L C Lc l o c k i n p u to u t p u to p t i o n f e e d b a c ki n p u to u t p u t01/14/19EECS 150, Fa07, Lec 26 - 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