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Berkeley COMPSCI 150 - Lec 15 – Storage: Regs, SRAM, ROM

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EECS 150 - Components and Design Techniques for Digital Systems Lec 15 – Storage: Regs, SRAM, ROMReview: TimingOutlineMemory BasicsDefinitionsRegister File InternalsRegid (address) DecodingAccessing Register FilesBasic Memory Subsystem Block DiagramMemory Components Types:Read Only Memory (ROM)Static RAM CellTypical SRAM Organization: 16-word x 4-bitSimplified SRAM timing diagramWhat happens when # bits gets largeInside a Tall-Thin RAM is a short-fat RAMColumn MUXAdministration and AnnouncementsRevised: Schedule of checkpointsLogic Diagram of a Typical SRAMCascading Memory Modules (or chips)Typical SRAM TimingMemory Blocks in FPGAsSynchronous SRAMVerilog for Virtex LUT RAMVirtex “Block RAMs”Multi-ported MemoryDual-ported Memory InternalsFirst-in-first-out (FIFO) MemoryFIFO InterfacesNon-volatile MemoryFLASH MemoryRelationship between Memory and CLA ROM as AND/OR Logic DevicePLD SummaryPLA ExamplePAL ExampleSummary1EECS 150 - Components and Design Techniques for Digital Systems Lec 15 – Storage: Regs, SRAM, ROM David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs1502Review: Timing•All gates have delays–RC delay in driving the output•Wires are distributed RCs–Delays goes with the square of the length•Source circuits determines strength–Serial vs parallel•Delays in combinational logic determine by –Input delay–Path length–Delay of each gate along the path–Worst case over all possible input-output paths•Setup and CLK-Q determined by the two latches in flipflop•Clock cycle : Tcycle  TCL+Tsetup+TclkQ + worst case skew•Delays can introduce glitches in combinational logic3Outline•Memory concepts•Register Files•SRAM•SRAM Access•Multiported Memories–FIFOS•ROM, EPROM, FLASH•Relationship to Comb. Logic4Memory Basics•Uses:Whenever a large collection of state elements is required. –data & program storage –general purpose registers –buffering –table lookups –CL implementation •Types:–RAM - random access memory –ROM - read only memory –EPROM, FLASH - electrically programmable read only memory •Example RAM: Register file from microprocessorregid = register identifier (address of word in memory)sizeof(regid) = log2(# of reg) WE = write enableclk5Definitions Memory Interfaces for Accessing Data •Asynchronous (unclocked): A change in the address results in data appearing •Synchronous (clocked): A change in address, followed by an edge on CLK results in data appearing or write operation occurring.A common arrangement is to have synchronous write operations and asynchronous read operations.•Volatile: Looses its state when the power goes off. •Nonvolatile:Retains it state when power goes off.6Register File Internals•For read operations, functionally the regfile is equivalent to a 2-D array of flip-flops with tristate outputs on each–MUX, but distributed–Unary control•Cell with added write logic:How do we go from "regid" to "SEL"? These circuits are just functional abstractions of the actual circuits used.7Regid (address) Decoding•The function of the address decoder is to generate a one-hot code word from the address.•Binary -> unary•Simplied DEMUX•The output is use for row selection.•Many different circuits exist for this function. A simple one is shown.•Where have you seen this before?8Accessing Register Files•Read: output is a combinational function of the address input–Change address, see data from a different word on the output–Regardless of clock•Write is synchronous–If enabled, input data is written to selected word on the clock edge•Often multi-ported (more on that later)addrdoutdinWEaddr XR[X]addr YR[Y]valclkval9Basic Memory Subsystem Block DiagramAddressDecoderWord Linen AddressBits2n wordlinesm Bit LinesMemorycellwhat happensif n and/or m isvery large?RAM/ROM naming convention: 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words10Memory Components Types:•Volatile:–Random Access Memory (RAM): »SRAM "static" »DRAM "dynamic" •Non-volatile:– Read Only Memory (ROM): » Mask ROM "mask programmable" »EPROM "electrically programmable" »EEPROM "erasable electrically programmable" »FLASH memory - similar to EEPROM with programmer integrated on chip11Read Only Memory (ROM)•Simplified form of memory. No write operation needed.•Functional Equivalence:•Full tri-state buffers are not needed at each cell point.•In practice, single transistors are used to implement zero cells. Logic one’s are derived through precharging or bit-line pullup transistor.Connections to Vdd used to store a logic 1, connections to GND for storing logic 0.address decoderbit-cell array12Static RAM Cell•Read:–1. Select row–2. Cell pulls one line low and one high–3. Sense output on bit and bit•Write:–1. Drive bit lines (e.g, bit=1, bit=0)–2. Select row•Why does this work?•When one bit-line is low, it will force output high; that will set new state6-Transistor SRAM Cellbit bitword(row select)100 113Typical SRAM Organization: 16-word x 4-bitSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCell- +Sense Amp- +Sense Amp- +Sense Amp- +Sense Amp: : : :Word 0Word 1Word 15Dout 0Dout 1Dout 2Dout 3- +Wr Driver - +Wr Driver - +Wr Driver - +Wr Driver Address DecoderWrEnDin 0Din 1Din 2Din 3A0A1A2A314Simplified SRAM timing diagram•Read: Valid address, then Chip Select•Access Time: address good to data valid–even if not visible on out•Cycle Time: min between subsequent mem operations•Write: Valid address and data with WE_l, then CS–Address must be stable a setup time before WE and CS go low–And hold time after one goes high•When do you drive, sample, or Z the data bus?15What happens when # bits gets large•Big slow decoder•Bit lines very log–Large distributed RC load•Treat output as differential signal, rather than rail-to-rail logic–Sense amps on puts–Can ‘precharge’ both bit lines high, so cell only has to pull one low•==> Make it shorter and widern bitsLog n bitaddress16Inside a Tall-Thin RAM is a short-fat RAM n = k x m bitsLog k bitaddressSense ampsmuxLog m bitaddress1 data bit17Column MUX •Controls physical aspect ratio –Important for physical layout and to control delay on wires.•In DRAM, allows time-multiplexing of chip address pins (later)18Administration and


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Berkeley COMPSCI 150 - Lec 15 – Storage: Regs, SRAM, ROM

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