EECS 150 - Components and Design Techniques for Digital Systems Lec 09 – Counters 9-28-04Review: Designing with FSMOutlineRegistersShift-registersShift RegisterShift Register VerilogShift Register ApplicationRegister with selective loadIQ: Design Register with Set/ResetCountersWhat are they used?How do we design counters?Slide 14Ring Counters – getting startedRing Counters (cont)AnnouncementsSynchronous CountersBinary CounterBinary Counter VerilogSlide 21Slide 22Slide 23Four-bit Binary Synchronous Up-Counter“Ripple” countersUp-Down CounterOdd CountsOffset CountersUniversal Shift RegisterDesign of Universal Shift RegisterUniversal Shift Register VerilogPattern RecognizerCounters for ControlRecall: Byte-bit stream with Rate MatchingCounter for Sequencing StatesCLR for “back to top”Count_Enable for Self-loopBranch with LD (jump counter)JumpingIQ: How would you simplify this furtherState Complexity vs Counter UsageAnother Controller using CountersCounter provides subsidiary stateSummaryEECS 150 - Components and Design Techniques for Digital Systems Lec 09 – Counters9-28-04 David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs1509/18/07EECS150 Fa07 Lec7 Counters2Review: Designing with FSM •FSMs are critical tool in your design toolbox–Adapters, Protocols, Datapath Controllers, …•They often interact with other FSMs•Important to design each well and to make them work together well.•Keep your verilog FSMs clean–Separate combinational part from state update•Good state machine design is an iterative process–State encoding–Reduction–Assignment9/18/07EECS150 Fa07 Lec7 Counters3Outline•Review•Registers•Simple, important FSMs–Ring counters–Binary Counters•Universal Shift Register•Using Counters to build controllers–Different approach to FSM design9/18/07EECS150 Fa07 Lec7 Counters4R S R S R SD Q D Q D Q D QOUT1 OUT2 OUT3 OUT4CLKIN1 IN2 IN3 IN4R S"0"Registers•Collections of flip-flops with similar controls and logic–Stored values somehow related (e.g., form binary value)–Share clock, reset, and set lines–Similar logic at each stage•Examples–Shift registers–Counters9/18/07EECS150 Fa07 Lec7 Counters5Shift-registers•Parallel load shift register:•“Parallel-to-serial converter”•Also, works as “Serial-to-parallel converter”, if Q values are connected out.•Also get used as controllers (ala “ring counters”)9/18/07EECS150 Fa07 Lec7 Counters6D Q D Q D Q D QINOUT1 OUT2 OUT3 OUT4CLKShift Registermodule shift_reg (out4, out3, out2, out1, in, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1;always @(posedge clk) begin out4 <= out3; out3 <= out2; out2 <= out1; out1 <= in; endendmoduleWhat does this shift register do?What is it good for?9/18/07EECS150 Fa07 Lec7 Counters7Shift Register Verilogmodule shift_reg (out, in, clk); output [4:1] out; input in, clk; reg [4:1] out;always @(posedge clk) begin out <= {out[3:1], in}; endendmodule9/18/07EECS150 Fa07 Lec7 Counters8parallel inputsparallel outputsserial transmissionShift Register Application•Parallel-to-serial conversion for serial transmission9/18/07EECS150 Fa07 Lec7 Counters9Register with selective load•We often use registers to hold values for multiple clocks–Wait until needed–Used multiple times•How do we modify our D flipflop so that it holds the value till we are done with it?•A very simple FSMclkDQenableDQenableclkEn State Next0 Q Q1 Q D9/18/07EECS150 Fa07 Lec7 Counters10IQ: Design Register with Set/Reset•Set forces state to 1•Reset forces state to 0•What might be a useful fourth option?DQS RS R State Next0 0 Q Q0 1 Q 01 0 Q 11 1 Q X9/18/07EECS150 Fa07 Lec7 Counters11Counters•Special sequential circuits (FSMs) that repeatedly sequence through a set of outputs. •Examples:–binary counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, …–gray code counter: 000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110, …–one-hot counter: 0001, 0010, 0100, 1000, 0001, 0010, …–BCD counter: 0000, 0001, 0010, …, 1001, 0000, 0001–pseudo-random sequence generators: 10, 01, 00, 11, 10, 01, 00, ...•Moore machines with “ring” structure to STD: S3S0S2S19/18/07EECS150 Fa07 Lec7 Counters12What are they used?•Examples:–Clock divider circuits–Delays, Timing–Protocols–Counters simplify controller design…»More on this later6416MHz9/18/07EECS150 Fa07 Lec7 Counters13How do we design counters?•For binary counters (most common case) incrementer circuit would work:•In Verilog, a counter is specified as: x = x+1;–This does not imply an adder–An incrementer is simpler than an adder–And a counter is simpler yet.•In general, the best way to understand counter design is to think of them as FSMs, and follow general procedure. Here’s a important examples…register+19/18/07EECS150 Fa07 Lec7 Counters14D Q D Q D Q D QINOUT1 OUT2 OUT3 OUT4CLKD Q D Q D Q D QINOUT1 OUT2 OUT3 OUT4CLKCounters•Sequences through a fixed set of patterns–In this case, 1000, 0100, 0010, 0001–If one of the patterns is its initial state (by loading or set/reset)•Mobius (or Johnson) counter–In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 00009/18/07EECS150 Fa07 Lec7 Counters15Ring Counters – getting started•“one-hot” counters0001, 0010, 0100, 1000, 0001, …“Self-starting” version:•What are these good for?DQDQDQDQq3q2q1q0DQDQDQDQq3q2q1S RS R S R S Rq0 0 0 0 0reset9/18/07EECS150 Fa07 Lec7 Counters16Ring Counters (cont)9/18/07EECS150 Fa07 Lec7 Counters17Announcements•Reading: K&B 7.1, app C. •Midterm 9/27 (week from thurs)–Regular class time. In Lab 125 Cory–Covers all material thru 9/23»9/23 lecture will be “putting it all together”•Review session 9/27 8-10–See web page for additional specifics•HW 3 (current) is a good exercise (and short)•HW 4 (out thurs) will be light, then skip a week•Thurs Evening Lab is a problem!–Too many people in that section–Too many people from other sections•Lab ‘DO NOT DISTURB’ rules–You much receive checkoff in your own section (first 30 mins)–You are welcome to use the lab outside your section, but if it is during some other lab section, you much let the TA concentrate on their section.
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