1University of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS150Fall 1998R. Fearing and Kevin ChoCheckpoint 2Video Interface1. ObjectiveIn this checkpoint, you will:1. Wire-up the Video Sync Separator, A/D Converter, video camera, and Op-amp2. Learn how to manipulate the A/D converter chip2. IntroductionThe video signal generated by the camera is a composite video signal. In this checkpoint, you will usethe LM1881 Sync Separator and the HI1175 Analog to Digital converter to build the video interface. TheLM1881 Video Sync Separator will help you to find out where the top and left edge of the image is, and theHI1175 A/D converter will convert the analog data from the video camera into 8 bits of digital data. Thiscan be stored into the SRAM. The logic analyzer will be used to check off your video interface.3. Wiring-up of the video interface3.1 Video CameraThe video camera used in the project is an NTSC standard camera. It generates an NTSC compatiblesignal, which was explained in the project specification sheet and is also shown in Figure 1. The camera isconnected to the Xilinx board through a 5 pin-DIN connector, which is located near the power plugs. Thepower of the camera is provided by the Xilinx board, thus you will need to wire up the power lines to thecamera from the nearest “+” and “-“ pins. After you finish wiring up the camera connector, you can checkif the camera works with an analog channel on the oscilloscope. At the video out pin of the camera, youshould see a waveform similar to (a) on Figure 1. For the camera DIN connector pinouts, look at thediagram on the camera housing.3.2 LM1881 Video Sync SeparatorThe LM1881 takes the composite video signal as an input, and provides outputs for vertical sync andcomposite sync, which can be used to find the beginning of a video frame and the beginning of a linerespectively. Refer to Figure 1 for the input to the LM1881 and the corresponding outputs - composite syncand vertical sync. For pinouts, refer to Figure 2.23.3 HI1175 A/D ConverterThe HI1175 is an 8-bit analog-to-digital converter. It takes analog input through the Vin pin, andoutputs an 8-bit digital output through D0 - D7 pins, which are tri-state buffered by OE.L pin. There is a2.5 clock cycle delay on the data. On every falling clock edge, the chip samples the analog input andoutputs a digital representation on the output pins after a 2.5 clock cycle + 18ns. You should use data onoutput pins three clock cycles after the sampling, falling edge. Refer to Figure 3 for the timing diagram.Its electrical interface is:• an analog input Vin• eight digital data outputs D0~D7• a clock input Clk • an active low output enable input OE.L – When OE.L = 0, Data is valid; When OE.L = 1, D0-D7 pinshigh impedance• a reference voltage (top) VRT which gives +2.6V if shorted with VRTS, the internal voltage reference(top)• a reference voltage(bottom) VBT which gives +0.6V if shorted with VBTS, the internal voltagereference(bottom)• digital power DVdd and digial ground DVss• analog power AVdd and analog ground AvssFor pinouts, refer to Figure 4.* Since the HI1175 has a different width than the chips that have been used in lab, a pin expander washanded out. When you wire up the A/D converter, don’t forget to use it.3.4 LT1213 Op AmpThe LT1213 is a dual, single-supply, precision op amp. In this checkpoint, only one op amp is used todouble the amplitude of the video signal. The op amp is configured in non-inverting mode, and the externalcircuitry set-up around the op amp, which is provided by RC network, accomplishes the amplification. Thebenefit of using the op amp as a pre-amp to the A/D converter is an improvement in the resolution per bit.This way, we get a clean, sharp image from the A/D converter. For pinouts, refer to Figure 5.3.5 RC NetworkThe RC network provides external miscellaneous circuitry for your LM1881 video sync separator,HI1175 A/D converter, and LT1213 op amp. For pinouts and the schematic of the RC network, refer toFigure 6. Wire up the video interface according to Fig.74. Testing the video interfaceWe provide a bit file Wvlib\cs150\check2.bit which can test your wiring. However, you need to buildyour own test circuit for the A/D converter. The top page Wvlib/cs150/sch/check.1 is provided for your testcircuit, which defines the input and output interface of the XILINX. To test the A/D converter, the OEshould be high to enable the A/D chip, and you also need to generate the clock signal VCLK for the A/Dconverter. The VCLK should have the frequency that you need for your horizontal resolution, i.e. 190, 210,or 230 pixels horizontally. Note that the clock signal CLK of your XILINX comes from the oscillator onyour board that has a frequency of 16MHz. As noted in the project spec, during one horizontal sync period- 63.5us, the real image signal comes only for 53.3us. Therefore, choose such a VCLK frequency that willallow you to sample a wider image as possible. Also, be careful not to skip a line. You should get at least80% of the image. Show your TA, with logic analyzer, the composite sync output and vertical sync output fromthe LM1881, and the CLK and D0~D7 of the A/D converter.3Figure 1. LM1881 Timing DiagramFigure 2. LM1881 Pinouts4Figure 3. HI1175 Timing DiagramFigure 5. LT1213 PinoutsFigure 4. HI1175 Pinouts5Figure 6. RC Network Pinout andSchematic0.1uF6Figure 7. Checkpoint2 Schematic7Name Name Lab Section (Check One)M: AM PM T: AM PM W: AM PM Th: PM5. Checkoffs1. Video Interface wired up ( neatly for full credit) (Due at the start of the lab session) TA: (30%)2. Functioning Sync Separator TA: (30%)3. Functioning A/D Converter TA: (40%)4. Turned in on timeTA: (100%) (full credit)5. Turned in one week lateTA: (50%) (half credit)----------------------------------------------Cut Here-----------------------------------------------------24 1234567891011122322212019181716151413Dvss OEVRB DVSSVRBS D0 (LSB)AVSS D1AVSS D2VIN D3AVDD D4VRT D5VRTS D6AVDD D7 (MSB)AVDD DVDDDVDD CLKHI117581726354VCC COMP SYNCO/D COMP VIDEORSET V SYNCBURST GNDLM188181726354VCC COMP SYNCO/D COMP VIDEORSET V SYNCBURST GNDLM188181726354V+ OUT AOUT B -IN A-IN B + IN A+IN B V-LT121381726354V+ OUT AOUT B -IN A-IN B + IN A+IN B
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