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Berkeley COMPSCI 150 - Lab Logistics & FPGA Editor

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1/24/20101Lab Logistics & FPGA EditorUCB EECS150 Spring 2010Lab Lecture #1Agenda• Lab Logistics– Lab lecture– Labs in general– Lab policies• Questions?• Class Hardware• FPGA Editor (CAD Tool)• Lab #1– Contents– Pre-lab• Questions?2UCB EECS150 Spring 2010, Lab Lecture #1Lab Lecture (1)• Components(1) Weekly quiz(2) ‘Lecturette’ from a T.A.• Motivation– Learn about the next week’s lab– Have a chance to ask questions• To get the most out of this…– Do the homework– Read the lab [before lab lecture]3UCB EECS150 Spring 2010, Lab Lecture #11/24/20102Lab Lecture (2)• Resources– In-lab HD audio & video, mic, projectors, CCTV– T.A. {him/her} self• Again, ask questions!• Sit where you can actually see the T.A.– Lab materials• Slides will be posted ahead of time• Lab *.zip file ~ contains:– Verilog, support files– Lab documents (+ what is required at check-off)4UCB EECS150 Spring 2010, Lab Lecture #1Labs (1)• Each lab consists of…(1) Lab lecture Friday (end of week 0)(2) Lab period Tues/Wed/Thurs* (week 1)(3) Check-off Tues/Wed/Thurs* (week 2)* During your assigned lab period• Check-off procedure– Lab T.A. will walk around the room in desk order– You are required to…(1) Show your T.A. the completed check-off sheet(2) Present all required demos5UCB EECS150 Spring 2010, Lab Lecture #1Labs (2)• Partner policy– The labs are about learning the tools… which everyone must do to pass this classLabs are done alone• Projects are done in groups of two– Odd enrollment handled on a case-by-case basis– Project Check-off• Partners should be able to attend the same lab• But do not have to be enrolled in the same lab• More details on this closer to the project6UCB EECS150 Spring 2010, Lab Lecture #11/24/20103Lab Policies (1)We all share the same lab.Treat it with care!• General Policies– At the lab stations• No food, drink, bikes, etc– At the white tables• Feel free to eat/drink• In all cases, clean up after yourself• This area will be used for discussion sections/office hours– Lab-wide• NO alcohol (all Campus policies apply)• Clean up your trash7UCB EECS150 Spring 2010, Lab Lecture #1Lab Policies (2)• Lab Usage– Section A/C*• EECS 150 has priority on space/computers• Feel free to work on other course work– Section B*• Being used for another class*: When in doubt: if the station doesn’t have an XUPv5, you won’t be able to use it!– T.A. Station: off-limits– Learn the lab orientation8UCB EECS150 Spring 2010, Lab Lecture #1Lab Policies (3)• Lab Access– Doors• Everyone should have cardkey right now– Check this – there isn’t any form to fill out• Don’t let others in (who knock)– Why, then, would we bother with cardkeys? – Computers• Standard EECS login forms (cs150-XY + password)• Logs into windows machines• Change your passwords (UNIX and Windows) ASAP• T.A.s will pass forms out after lab lecture today9UCB EECS150 Spring 2010, Lab Lecture #11/24/20104Lab Policies (4)• Lab Media– Printing• Three printers (A, B, C)• Computers will automatically print to nearest printer• Don’t waste paper – this is Berkeley after all– Storage• C:/ – fast & volatile. – Do: Store/run temporary/[automatically generated] project files– Don’t: Store code (it will get deleted upon logging out)• U:/ – slow & non-volatile. – Do: Store code (it won’t get deleted)– Don’t: Run the tools (they will run slowly)• SVN – submissions & project. – Do: Use in favor of U:/– Don’t: Commit temporary project files (we’ve seen 600 GB of garbage)– Will be setup shortly10UCB EECS150 Spring 2010, Lab Lecture #1Lab Policies (5)• Lab Design Platform– “XUPv5/ML505” (board) – LX110T-1 (FPGA)– New as of Spring 2009– Treat with extreme care!• Our last board (CaLinx) lasted 8 years• We’d like the XUPv5 to do the same** Fine print: if we catch you intentionally damaging the boards (penciling ICs, you name it), your lab access will be revoked and your standing put in jeopardy. This includes what your friends (who aren’t in the class but who you have let into the lab) do to the boards. We have cameras!UCB EECS150 Spring 2010, Lab Lecture #1 11Lab Policies (6)• Lab Resources– Are the same as the class’ resources– Website: http://inst.eecs.berkeley.edu/~cs150/sp10/– Newsgroup: https://inst.eecs.berkeley.edu/~webnews/webnews.cgi– Your T.A.s– Your peers• The T.A.s won’t always be here (fact!)12UCB EECS150 Spring 2010, Lab Lecture #11/24/20105Questions?• Lab Lecture– Components– Expectations• Lab Format– Components– Check-off• Logistics– General lab policies– Lab {Usage, Access, Media, Platform, Resources}UCB EECS150 Spring 2010, Lab Lecture #1 13FPGA Editor (1)• What is FPGA Editor?“A graphical application for designing to & configuring FPGAs”– Design directly to the FPGA fabric– Very little CAD abstraction• No SPICE-like code (It’s a GUI) Just LUTs, SLICEs, CLBs, etc– FPGA Editor makes working with an FPGA roughly equivalent to working with a {proto, bread} boardUCB EECS150 Spring 2010, Lab Lecture #1 14FPGA Editor (2)Fabric4x CLBSLICE• Why bother?– In CS150• Introduction to FPGA architecture & hierarchy– In Industry• Design optimization• Debugging, Hard Macro IP– You will be working throughan abstraction (Verilog HDL*)for much of the semester* Hardware Description LanguageUCB EECS150 Spring 2010, Lab Lecture #1 15vs.1/24/20106FPGA Editor (3)• Capabilities– Hand-route a design• Optimization, tuning– Faster debugging(1) Manually route a wire (or “net”) to a pin on the FPGA(2) Use an Oscilloscope/etc to probe the net– Bypass shortcomings of the embedded era• Old days: O-scope probe any signal you like• Modern days: Everything is embedded! You can’t scope anything!UCB EECS150 Spring 2010, Lab Lecture #1 16Lab 1 (1)• Design with FPGA Editor• You will learn how to…(1) Navigate the FPGA hierarchy(2) Program LUTs directly(3) Hand-route additional features into your design• Explore a part of the CAD flowUCB EECS150 Spring 2010, Lab Lecture #1 17Lab 1 (2)CAD Flow (Big Picture)UCB EECS150 Spring 2010, Lab Lecture #1 18010110001001001101000101010100100101Translate/Map/PARFPGA EditorBitGeniMPACT.ncd.ncd.ncd (optionally modified).bitDesign PartitioningDesign EntryBehavioral Verilog HDLSynplify ProOptional stepLogic SynthesisSynplify


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