CS 150 - Spring 2007 – Lecture #29: Recap - 1Course Wrap-up! Priority Encoder Revisited! What (We Hope) You Learned! Design Methodology! Final Exam InformationCS 150 - Spring 2007 – Lecture #29: Recap - 2Let’s Try the Priority Encoder One More Time …I3I2I1I0O3O2O1O0Zero0KIKO01IjOjKOKIKI01OjIj0KOIj1=0=1CS 150 - Spring 2007 – Lecture #29: Recap - 3Let’s Try the Priority Encoder One More Time …01100KIKO001100110001100000KIKO000000010KIKO00100000001001CS 150 - Spring 2007 – Lecture #29: Recap - 4What we HOPE you learned in CS 150 …! Language of logic design" Logic optimization, state, timing, CAD tools! Concept of state in digital systems" Analogous to variables and program counters in software systems! Hardware system building" Datapath + control = digital systems! Hardware system design methodology" Hardware description languages: Verilog" Tools to simulate design behavior: output = function (inputs)" Logic compilers synthesize hardware blocks of our designs" Mapping onto programmable hardware (code generation)! Contrast with software design" Both map specifications to physical devices" Both must be flawless…the price we pay for using discrete mathCS 150 - Spring 2007 – Lecture #29: Recap - 5Current state of digital design! Changes in industrial practice" Larger designs" Shorter time to market" Cheaper products! Scale" Pervasive use of computer-aided design tools over hand methods" Multiple levels of design representation! Time" Emphasis on abstract design representations" Programmable rather than fixed function components" Automatic synthesis techniques" Importance of sound design methodologies! Cost" Higher levels of integration" Use of simulation to debug designsCS 150 - Spring 2007 – Lecture #29: Recap - 6New ability: to accomplish the logic design task with the aid of computer-aideddesign tools and map a problem description into an implementation withprogrammable logic devices after validation via simulation and understandingof the advantages/disadvantages as compared to a software implementationCS 150: concepts/skills/abilities! Basics of logic design (concepts)! Sound design methodologies (concepts)! Modern specification methods (concepts)! Familiarity with full set of CAD tools (skills)! Appreciation for differences and similarities(abilities) in hardware and software designCS 150 - Spring 2007 – Lecture #29: Recap - 7Representation of Digital Designs! Physical devices (transistors, relays)!Switches!Truth tables!Boolean algebra!Gates! Waveforms! Finite state behavior! Register-transfer behavior! Concurrent abstract specificationsSimulation, Chipscope& Complex SystemDescription (e.g., SDRAM)VerilogStructural & BehaviorialDescriptionsCS 150 - Spring 2007 – Lecture #29: Recap - 8Digital System Design! Door combination lock:" Punch in 3 values in sequence and the door opens; if there is anerror the lock must be reset; once the door opens the lock must bereset" Inputs: sequence of input values, reset" Outputs: door open/close" Memory: must remember combinationor always have it available as an inputCS 150 - Spring 2007 – Lecture #29: Recap - 9Implementation in Softwareinteger combination_lock ( ) {integer v1, v2, v3;integer error = 0;static integer c[3] = 3, 4, 2;while (!new_value( ));v1 = read_value( );if (v1 != c[1]) then error = 1;while (!new_value( ));v2 = read_value( );if (v2 != c[2]) then error = 1;while (!new_value( ));v3 = read_value( );if (v2 != c[3]) then error = 1;if (error == 1) then return(0); else return (1);}CS 150 - Spring 2007 – Lecture #29: Recap - 10Implementation as a Sequential Digital System! Encoding:" How many bits per input value?" How many values in sequence?" How do we know a new input value is entered?" How do we represent the states of the system?! Behavior:" Clock wire tells us when it’s ok to look at inputs(i.e., they have settled after change)" Sequential: sequence of values must be entered" Sequential: remember if an error occurred" Finite-state specificationresetvalueopen/closednewclockstateCS 150 - Spring 2007 – Lecture #29: Recap - 11closed closedclosedC1=value& newC2=value& newC3=value& newC1!=value& newC2!=value& newC3!=value& newclosedresetnot newnot newnot newS1 S2 S3 OPENERRopenSequential Example (cont’d):Abstract Control! Finite-state Diagram" States: 5 states# Represent point in execution of machine# Each state has outputs" Transitions: 6 from state to state, 5 self transitions, 1 global# Changes of state occur when clock says it’s ok# Based on value of inputs" Inputs: reset, new, results of comparisons" Output: open/closedCS 150 - Spring 2007 – Lecture #29: Recap - 12resetopen/closednewC1 C2 C3comparatorvalueequalmultiplexerequalcontrollermux controlclockSequential Example (cont’d):Data-path vs. Control! Internal Structure" Data-path# Storage for combination# Comparators" Control# Finite-state machine controller# Control for data-path# State changes controlled by clockCS 150 - Spring 2007 – Lecture #29: Recap - 13closedclosedmux=C1resetequal& newnot equal& newnot equal& newnot equal& newnot newnot newnot newS1 S2 S3 OPENERRclosedmux=C2equal& newclosedmux=C3equal& newopenSequential Example (cont’d):Finite-state Machine! Finite-state Machine" Refine state diagram to include internal structureCS 150 - Spring 2007 – Lecture #29: Recap - 14reset new equal state state mux open/closed1 – – – S1 C1 closed0 0 – S1 S1 C1 closed0 1 0 S1 ERR – closed0 1 1 S1 S2 C2 closed0 0 – S2 S2 C2 closed0 1 0 S2 ERR – closed0 1 1 S2 S3 C3 closed0 0 – S3 S3 C3 closed0 1 0 S3 ERR – closed0 1 1 S3 OPEN – open 0 – – OPEN OPEN – open0 – – ERR ERR – closednextSequential Example (cont’d):Finite-state Machine! Finite-state Machine" Generate state table (much like a truth-table)closedclosedmux=C1resetequal& newnot equal& newnot equal& newnot equal& newnot newnot newnot newS1 S2 S3 OPENERRclosedmux=C2equal& newclosedmux=C3equal& newopenCS 150 - Spring 2007 – Lecture #29: Recap - 15Sequential Example (cont’d):Encoding! Encode State Table" State can be: S1, S2, S3, OPEN, or ERR# Needs at least 3 bits to encode: 000, 001, 010, 011, 100# And as many as 5: 00001, 00010, 00100, 01000, 10000# Choose 4 bits: 0001, 0010, 0100, 1000, 0000" Output mux can be: C1, C2, or C3# needs 2 to 3 bits to encode# choose 3 bits: 001, 010, 100" Output open/closed can be: open or closed# needs 1 or 2 bits to encode# choose 1 bits: 1, 0CS 150 - Spring 2007 – Lecture #29: Recap - 16good choice of
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