1Spring 2002 EECS150 - Lec02-CMOSPage 1EECS150 - Digital DesignLecture 2 - CMOSJanuary 24, 2002John WawrzynekSpring 2002 EECS150 - Lec02-CMOSPage 2Outline• Overview of Physical Implementations• CMOS devices• Announcements/Break• CMOS transistor circuits– basic logic gates– tri-state buffers– flip-flops• flip-flop timing basics• circuits• example useSpring 2002 EECS150 - Lec02-CMOSPage 3Overview of Physical Implementations• Integrated Circuits (ICs)– CL, memory elements, analog interfaces. • Printed Circuits (PC) boards– substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation. • Power Supplies– Converts line AC voltage to regulated DC low voltage levels. • Chassis (rack, card case, ...) – holds boards, power supply, provides physical interface to user or other systems. • Connectors and Cables. The stuff out of which we make systems.Spring 2002 EECS150 - Lec02-CMOSPage 4Integrated Circuits• Primarily Crystalline Silicon• 1mm - 25mm on a side• 100 - 100M transistors• (25 - 25M "gates")• 3 - 10 conductive layers• 2002 - feature size ~ 0.13um = 0.13 x 10-6m • “CMOS” most common -complementary metal oxide semiconductor• Package provides:– spreading of chip-level signal paths to board-level – heat dissipation. • Ceramic or plastic with gold wires. Chip in PackageSpring 2002 EECS150 - Lec02-CMOSPage 5Printed Circuit Boards• fiberglass or ceramic• 1-20 conductive layers • 1-20in on a side • IC packages are soldered down.Multichip Modules (MCMs)• Multiple chips cirectly connected to a substrate. (silicon, ceramic, plastic, fiberglass) without chip packages.Spring 2002 EECS150 - Lec02-CMOSPage 6Integrated Circuits• Moore’s Law has fueled innovation for the last 3 decades.• “Number of transistors on a die doubles every 18 months.”• What are the side effects of Moore’s law?2Spring 2002 EECS150 - Lec02-CMOSPage 7Integrated Circuits• Uses for digital IC technology today:– standard microprocessors• used in desktop PCs, and embedded applications• simple system design (mostly software development)– memory chips (DRAM, SRAM)– application specific ICs (ASICs)• custom designed to match particular application• can be optimized for low-power, low-cost, high-performance• high-design cost– field programmable logic devices (FPGAs, CPLDs)• customized to particular application• short time to market• relatively high part cost– standardized low-density components• still manufactured for compatibility with older system designsSpring 2002 EECS150 - Lec02-CMOSPage 8CMOS DevicesCross SectionThe gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation the device acts like a switch.Top View• MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Spring 2002 EECS150 - Lec02-CMOSPage 9Announcements• If you are enrolled and plan to take the course you must attend your lab section next week, otherwise will be dropped from the class roster.• Please note:Thursday morning lab section will not be held. If you are enrolled in that lab section, please change (using Telebears) to a different lab before next week. If you are on the wait list and would like to get into the class you must:1 Turn in an appeal for on third floor Soda.2 Attend lectures and do the homework, the first two weeks. 3 In the second week of classes, go to the lab section in which you wish to enroll. Give the TA your name and student ID. 4 Later, we will process the waitlist based on these requests, and lab section openings. Æ The final class roster will be posted at noon on Friday Feb 1.Spring 2002 EECS150 - Lec02-CMOSPage 10Announcements Lectures are being taped and will be available for viewing through CalView in McLaughlin Hall. Reading assignment for this week. All of chapter 1 Chapter 10 sections 1,2,7,8,9 Homework exercises will be posted later today.Spring 2002 EECS150 - Lec02-CMOSPage 11Transistor-level Logic Circuits• Inverter (NOT gate): • NAND gateHow about AND gate?Spring 2002 EECS150 - Lec02-CMOSPage 12Transistor-level Logic Circuits• NAND gate • NOR gate3Spring 2002 EECS150 - Lec02-CMOSPage 13Transistor-level Logic Circuits• Transistor circuit“high impedance” (output disconnected)• Variations• Tri-state BufferSpring 2002 EECS150 - Lec02-CMOSPage 14Transistor-level Logic Circuits• MultiplexorIf s=1 then c=a else c=b• Transistor CircuitSpring 2002 EECS150 - Lec02-CMOSPage 15D-type edge-triggered flip-flop• The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering). – At all other times the output Q is independent of the input D (just stores previously sampled value). – The input must be stable for a short time before the clock edge. Spring 2002 EECS150 - Lec02-CMOSPage 16Parallel to Serial Converter Example• 4-bit version:• Operation:– cycle 1: load x, output x0– cycle i: output xiif LD=1 load FF from xielse from previous stage.• Each stage:Spring 2002 EECS150 - Lec02-CMOSPage 17Parallel to Serial Converter Example• timing:Spring 2002 EECS150 - Lec02-CMOSPage 18Transistor-level Logic Circuits• Level-sensitive latch• Edge-triggered
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