1Spring 2002 EECS150 - Lec19-memory Page 1EECS150 - Digital DesignLecture 20 - MemoryApril 4&9, 2002John WawrzynekSpring 2002 EECS150 - Lec19-memory Page 2Memory Basics• Uses:– data & program storage– general purpose registers– buffering– table lookups– CL implementation– Whenever a large collection ofstate elements is required.• Types:– RAM - random access memory– ROM - read only memory– EPROM, FLASH - electricallyprogrammable read onlymemeory• Example RAM: Register fileregid = register identifiersizeof(regid) = log2(# of reg)WE = write enableSpring 2002 EECS150 - Lec19-memory Page 3Register File Internals• Functionally the regfile isequivalent to a 2-D arrayof flip-flops:• Cell with write logic:How do we go from "regid" to "SEL"? Spring 2002 EECS150 - Lec19-memory Page 4Regid (address) DecodingSpring 2002 EECS150 - Lec19-memory Page 5Standard Internal Memory Organization• Special circuit tricks are used for the cell array to improve storagedensity. (We will look at these later)• RAM/ROM naming convention:– examples: 32 X 8, "32 by 8" => 32 8-bit words– 1M X 1, "1 meg by 1" => 1M 1-bit wordsSpring 2002 EECS150 - Lec19-memory Page 6Read Only Memory (ROM)• Functional Equivalence:• Of course, full tri-state buffers are not needed at each cell point.• Single transistors are used to implement zero cells. Logic one’s arederived through precharging or bit-line pullup transistor.2Spring 2002 EECS150 - Lec19-memory Page 7Column MUX in ROMs and RAMs:• Controls physical aspect ratio• In DRAM, allows reuse of chip address pinsSpring 2002 EECS150 - Lec19-memory Page 8Cascading Memory Modules (or chips)• example 256 X 8 ROM using256 X 4 parts:• example: 1K X * ROM using 256X 4 parts:• each module has tri-stateoutputs:Spring 2002 EECS150 - Lec19-memory Page 9Definitions• Bandwidth:Total amount of data accross out of a device or across an interface per unittime. (usually Bytes/sec)• Latency:A measure of the time from a request for a data transfer until the data isreceived.Memory Interfaces for Acessing Data• Asynchronous (unclocked):A change in the address results in data appearing• Synchronous (clocked):A change in address, followed by an edge on CLK results in data appearing.Somtimes, multiple request may be outstanding.• Volatile:Looses its state when the power goes off.Spring 2002 EECS150 - Lec19-memory Page 10Example Memory Components:• Volatile:– Random Access Memory (RAM):• DRAM "dynamic"• SRAM "static"• Non-volatile:– Read Only Memory (ROM):• Mask ROM "mask programmable"• EPROM "electrically programmable"• EEPROM "erasable electrically programmable"• FLASH memory - similar to EEPROM with programmer integrated onchipSpring 2002 EECS150 - Lec19-memory Page 11Volatile Memory Comparison• SRAM Cell• Larger cell ⇒ lower density, highercost/bit• No refresh required• Simple read ⇒ faster access• Standard IC process ⇒ natural forintegration with logic• DRAM Cell• Smaller cell ⇒ higher density, lowercost/bit• Needs periodic refresh, and refreshafter read• Complex read ⇒ longer access time• Special IC process ⇒ difficult tointegrate with logic circuitsword linebit linebit lineword linebit lineSpring 2002 EECS150 - Lec19-memory Page 12In Desktop Computer Systems:• SRAM (lower density, higherspeed) used in CPU register file,on- and off-chip caches.• DRAM (higher density, lowerspeed) used in main memory• Closing the GAP: Innovation targeted towards higher bandwidth formemory systems:– SDRAM - synchronous DRAM– RDRAM - Rambus DRAM– EDORAM - extended data out SRAM – Three-dimensional RAM– hyper-page mode DRAM video RAM– multibank DRAM3Spring 2002 EECS150 - Lec19-memory Page 13Important DRAM Examples:• EDO - extended data out (similar to fast-page mode)– RAS cycle fetched rows of data from cell array blocks (long access time,around 100ns)– Subsequent CAS cycles quickly access data from row buffers if within anaddress page (page is around 256 Bytes)• SDRAM - synchronous DRAM– clocked interface– uses dual banks internally. Start access in one back then next, thenreceive data from first then second.• DDR - Double data rate SDRAM– Uses both rising (positive edge) and falling (negative) edge of clock fordata transfer. (typical 100MHz clock with 200 MHz transfer).• RDRAM - Rambus DRAM– Entire data blocks are access and transferred out on a highspeed bus-likeinterface (500 MB/s, 1.6 GB/s)– Tricky system level design. More expensive memory chips.Spring 2002 EECS150 - Lec19-memory Page 14Non-volatile Memory• Mask ROM– Used with logic circuits for tables etc.– Contents fixed at IC fab time (truly write once!)• EPROM (erasable programmable) & FLASH– requires special IC process(floating gate technology)– writing is slower than RAM. EPROM uses special programming system toprovide special voltages and timing.– reading can be made fairly fast.– rewriting is very slow.• erasure is first required , EPROM - UV light exposureUsed to hold fixed code (ex. BIOS), tables of data (ex. FSM next state/outputlogic), slowly changing values (date/time on computer)Spring 2002 EECS150 - Lec19-memory Page 15FLASH Memory• Electrically erasable• In system programmability and erasability (no special system orvoltages needed)• On-chip circuitry (FSM) to control erasure and programming (writing)• Erasure happens in variable sized "sectors" in a flash (16K - 64KBytes)See: http://developer.intel.com/design/flash/for product descriptions, etc.Spring 2002 EECS150 - Lec19-memory Page 16Relationship between Memory and CL• Memory blocks can be (andoften are) used to implementcombinational logic functions:• Examples:– LUTs in FPGAs– 1Mbit x 8 EPROM canimplement 8 independentfunctions each of log2(1M)=20inputs.• The decoder part of a memoryblock can be considered a“minterm generator”.• The cell array part of a memoryblock can be considered an ORfunction over a subset of rows.• The combination gives us a wayto implement logic functionsdirectly in sum of products form.• Several variations on this themeexist in a set of devices calledProgrammable logic devices(PLDs)Spring 2002 EECS150 - Lec19-memory Page 17A ROM as AND/OR Logic DeviceSpring 2002 EECS150 - Lec19-memory Page 18PLD Summary4Spring 2002 EECS150 - Lec19-memory Page 19PLA ExampleSpring 2002 EECS150 - Lec19-memory Page 20PAL ExampleSpring 2002 EECS150 - Lec19-memory Page 21Memory Blocks
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