EECS150 Spring 2005 Lab6 UCB 1 2005 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 6 Logic Analyzers 1.0 Motivation In the last lab, you had a chance to become familiar with the basic debugging techniques which will allow you to finish your project in this course. This week you are being asked to work with more sophisticated hardware debugging tools: the HP/Agilent Logic Analyzers and Xilinx’s software logic analyzer: ChipScope. Logic analyzers are the most powerful tool available for debugging digital circuits, they can potentially show every signal in your circuit on every clock cycle. As you might expect this power comes with a price: using a logic analyzer requires practice, therefore it is the goal of this lab to help you gain experience with these powerful tools before you need to work on your final project. 2.0 Introduction In this lab you will be working with two tools, the first of which is the bench logic analyzer from HP/Agilent. These bench analyzers use specialized probes and expensive hardware to capture digital signals from your circuit. The main virtue of these analyzers is their ability to zoom in and out in time, so as to see the operation of your circuit over long time periods (10msec). As good as there are however these logic analyzers are expensive and have some drawbacks, hence the second tool you will use. You will debug a broken counter circuit in the FPGA using a software-based logic analyzer called ChipScope. The bench logic analyzers in the lab only have 16 binary channels, which is often insufficient for debugging more complicated designs. In addition, it is sometimes hard to set the correct triggering modes and get the data you need from these logic analyzers. Thankfully, Xilinx offers ChipScope, which will allow you to integrate a logic analyzer with your design and then control it from the computer. With ChipScope you can examine significantly more than 16 signals, use more powerful triggering modes, and even save the data for later analysis. 3.0 Prelab Please make sure to complete the prelab before you attend your lab section. You will not be able to finish this lab in 3hrs otherwise! 1. Read this handout thoroughly. Pay particular attention to section 4.0 Lab Procedure as it describes what you will be doing in detail. 2. Examine the Verilog provided for this weeks lab.EECS150 Spring 2005 Lab6 UCB 2 2005 a. You should become intimately familiar with the FPGA_TOP2.v files as you will need to debug with it. b. Watch the ChipScope tutorial, examine the example verilog i. http://www-inst.eecs.berkeley.edu/~cs150/sp05/Documents.htm#Tutorials 3. You will need the entire 3hr lab! a. You will need to test and debug both your verilog and ours. b. You will be asked to use the logic analyzer for the first time. c. You will be asked to use the ChipScope for the first time. i. It’s easy to use, but you will need to play with it to learn it 4.0 Lab Procedure 4.1 Bench Analyzer In this part of the lab you will be examining an FSM, similar to Part 3 of Lab #5. However this time you will not have the luxury of being able to single step through the various states. This FSM has no enable signal, and will therefore take an input on every clock cycle. At 27MHz, this means that it could potentially go through 27 million states per second, much too quickly for you to observe on the LEDs, let alone record. Shown in Figure 5 below is a high level block diagram of the test harness we have built for you in FPGA_TOP2. Your job is to connect the logic analyzer at your station to the pins listed in parentheses, set up a pattern of 8 inputs to be fed to the FSM and then push Reset (SW1). This will reset the FSM and then feed it those 8 inputs in a continuous loop, allowing you to trace through the various FSM states on the logic analyzer. Figure 1: Lab #6 Part1 Test Harness We have provided you with the code for this test harness and the shifter, please read the code thoroughly as it will make your job during lab significantly easier. We have again given you only a black box for the FSM. For more information about working with black boxes, see section 4.2 in Lab #5.EECS150 Spring 2005 Lab6 UCB 3 2005 You job is to derive a complete bubble-and-arc diagram for this FSM. Keep in mind that one input pattern may show you most of the FSM. This FSM uses all 8 states, you must find and label all 16 arcs as well as the outputs. PLEASE READ SECTION 5.0 HP54645D Mixed Signal Oscilloscope (Logic Analyzer) CAREFULLY! TAKE SPECIAL NOTE OF 5.1.8 Digital, 5.1.9 Trigger AND 5.1.10 Storage NOT TO MENTION 5.2 Triggering. 4.2 ChipScope Integrated Logic Analyzer For this part of the lab we have provided you will two counters: Counter and BrokenCounter. They should be functionally identical, however as you might guess BrokenCounter is very buggy. It is your job to figure out what the BrokenCounter is actually doing. The easiest way to do this will be to instantiate both counters in FPGA_TOP2+.V and then compare their output. When their output is not equal you will want to trigger the ChipScope logic analyzer. You must fill in FPGA_TOP2+ with the testing harness needed to determine what BrokenCounter is actually doing. Your goal for this part of the lab is to tell us what the problem with BrokenCounter is, using only a verilog test harness of your own design and ChipScope. We recommend that you work with the ChipScope example and walkthrough available on the documents page of the CS150 website at http://www-inst.eecs.berkeley.edu/~cs150/sp05/Documents.htm#Tutorials. 4.2.1 Working with ChipScope ChipScope is an embedded, software based logic analyzer. By inserting an “integrated controller core” (icon) and an “integrated logic analyzer” (ila) into your design and connecting them properly, you can monitor any or all of the signals in your design. ChipScope provides you with a convenient software based interface for controlling the “integrated logic analyzer,” including setting the triggering options and viewing the
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