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1Fall 2002 EECS150 - Lec16-mem1Page 1EECS150 - Digital DesignLecture 16 - MemoryOctober 17, 2002John WawrzynekFall 2002 EECS150 - Lec16-mem1Page 2Memory Basics• Uses:– data & program storage – general purpose registers – buffering – table lookups – CL implementation – Whenever a large collection of state elements is required. • Types:– RAM - random access memory – ROM - read only memory – EPROM, FLASH - electrically programmable read onlymemeory • Example RAM: Register fileregid = register identifiersizeof(regid) = log2(# of reg) WE = write enable2Fall 2002 EECS150 - Lec16-mem1Page 3Definitions Memory Interfaces for Acessing Data• Asynchronous (unclocked): A change in the address results in data appearing • Synchronous (clocked): A change in address, followed by an edge on CLK results in data appearing or write operation occuring.• Volatile:Looses its state when the power goes off. Fall 2002 EECS150 - Lec16-mem1Page 4Register File Internals• Functionally the regfile is equivalent to a 2-D array of flip-flops:• Cell with write logic:How do we go from "regid" to "SEL"?3Fall 2002 EECS150 - Lec16-mem1Page 5Regid (address) DecodingFall 2002 EECS150 - Lec16-mem1Page 6Standard Internal Memory Organization • Special circuit tricks are used for the cell array to improve storage density. (We will look at these later)• RAM/ROM naming convention: – examples: 32 X 8, "32 by 8" => 32 8-bit words – 1M X 1, "1 meg by 1" => 1M 1-bit words4Fall 2002 EECS150 - Lec16-mem1Page 7Read Only Memory (ROM)• Functional Equivalence:• Of course, full tri-state buffers are not needed at each cell point.• Single transistors are used to implement zero cells. Logic one’s are derived through precharging or bit-line pullup transistor.Fall 2002 EECS150 - Lec16-mem1Page 8Column MUX in ROMs and RAMs: • Controls physical aspect ratio • In DRAM, allows reuse of chip address pins5Fall 2002 EECS150 - Lec16-mem1Page 9Cascading Memory Modules (or chips) • example 256 X 8 ROM using 256 X 4 parts:• example: 1K X * ROM using 256 X 4 parts:• each module has tri-state outputs: Fall 2002 EECS150 - Lec16-mem1Page 10Example Memory Components:• Volatile:– Random Access Memory (RAM): • DRAM "dynamic" • SRAM "static" • Non-volatile:– Read Only Memory (ROM): • Mask ROM "mask programmable" • EPROM "electrically programmable" • EEPROM "erasable electrically programmable" • FLASH memory - similar to EEPROM with programmer integrated on chip6Fall 2002 EECS150 - Lec16-mem1Page 11Volatile Memory Comparison • SRAM Cell• Larger cell ⇒ lower density, higher cost/bit • No refresh required • Simple read ⇒ faster access • Standard IC process ⇒ natural for integration with logic• DRAM Cell• Smaller cell ⇒ higher density, lower cost/bit • Needs periodic refresh, and refresh after read • Complex read ⇒ longer access time • Special IC process ⇒ difficult to integrate with logic circuitsword linebit linebit lineword linebit lineFall 2002 EECS150 - Lec16-mem1Page 12Multi-ported Memory• Motivation:– Consider CPU core register file:• 1 read or write per cycle limits processor performance.• Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile.• Common arrangement in pipelined CPUs is 2 read ports and 1 write port.databufferdisk/networkCPU• Motivation:– I/O data buffering:• dual-porting allows both sides to simultaneously access memory at full bandwidth. addradataaRWaaddrbdatabRWbDual-portMemoryselaselbselcdataadatabdatacRegfile7Fall 2002 EECS150 - Lec16-mem1Page 13Dual-ported Memory Internals• Add decoder, another set of read/write logic, bits lines, word lines:• Example cell: SRAM• Repeat everything but cross-coupled inverters.• This scheme extends up to a couple more ports, then need to add additional transistors.decadecbcellarrayr/w logicr/w logicdata portsaddressportsb2b2b1b1WL2WL1Fall 2002 EECS150 - Lec16-mem1Page 14In Desktop Computer Systems: • SRAM (lower density, higher speed) used in CPU register file, on- and off-chip caches.• DRAM (higher density, lower speed) used in main memory• Closing the GAP: Innovation targeted towards higher bandwidth for memory systems: – SDRAM - synchronous DRAM – RDRAM - Rambus DRAM – EDORAM - extended data out SRAM – Three-dimensional RAM – hyper-page mode DRAM video RAM – multibank DRAM8Fall 2002 EECS150 - Lec16-mem1Page 15Important DRAM Examples:• EDO - extended data out (similar to fast-page mode) – RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns)– Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) • SDRAM - synchronous DRAM– clocked interface – uses dual banks internally. Start access in one back then next, then receive data from first then second. • DDR - Double data rate SDRAM – Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). • RDRAM - Rambus DRAM – Entire data blocks are access and transferred out on a highspeed bus-like interface (500 MB/s, 1.6 GB/s) – Tricky system level design. More expensive memory chips. Fall 2002 EECS150 - Lec16-mem1Page 16Non-volatile Memory •Mask ROM – Used with logic circuits for tables etc.– Contents fixed at IC fab time (truly write once!) • EPROM (erasable programmable)& FLASH – requires special IC process (floating gate technology) – writing is slower than RAM. EPROM uses special programming system to provide special voltages and timing. – reading can be made fairly fast.– rewriting is very slow. • erasure is first required , EPROM - UV light exposure Used to hold fixed code (ex. BIOS), tables of data (ex. FSM next state/output logic), slowly changing values (date/time on computer)9Fall 2002 EECS150 - Lec16-mem1Page 17FLASH Memory • Electrically erasable • In system programmability and erasability (no special system or voltages needed) • On-chip circuitry (FSM) to control erasure and programming (writing) • Erasure happens in variable sized "sectors" in a flash (16K - 64K Bytes) See: http://developer.intel.com/design/flash/for product descriptions, etc.Fall 2002 EECS150 - Lec16-mem1Page 18Memory Specification in Verilog• Memory modeled by an array of registers:reg[15:0] memword[0:1023]; // 1,024 registers of 16 bits


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Berkeley COMPSCI 150 - Memory

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