CS152 Computer Architecture and Engineering Lecture 23 Virtual Memory Buses and I O 1 April 28 2003 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Recall Cache Performance Execution Time Instruction Count x Cycle Time x ideal CPI Memory Stalls Inst Other Stalls Inst Memory Stalls Inst Instruction Miss Rate x Instruction Miss Penalty Loads Inst x Load Miss Rate x Load Miss Penalty Stores Inst x Store Miss Rate x Store Miss Penalty Average Memory Access time AMAT Hit TimeL1 Miss RateL1 x Miss PenaltyL1 Hit RateL1 x Hit TimeL1 Miss RateL1 x Miss TimeL1 Average Memory Access time Hit Time Miss Rate x Miss Penalty 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Recall Cache techniques Caches TLBs Virtual Memory all understood by examining how they deal with 4 questions 1 Where can block be placed 2 How is block found 3 What block is replaced on miss 4 How are writes handled Techniques people use to improve the miss rate of caches Technique MR MP HT Complexity Larger Block Size Higher Associativity Victim Caches 2 Pseudo Associative Caches HW Prefetching of Instr Data Compiler Controlled Prefetching Compiler Reduce Misses 4 28 03 UCB Spring 2003 0 1 2 2 3 0 CS152 Kubiatowicz Recall Reducing Misses via a Victim Cache How to combine fast hit time of direct mapped yet still avoid conflict misses Add buffer to place data discarded from cache Jouppi 1990 4 entry victim cache removed 20 to 95 of conflicts for a 4 KB direct mapped data cache Used in Alpha HP machines TAGS DATA Tag and Comparator One Cache line of Data Tag and Comparator One Cache line of Data Tag and Comparator One Cache line of Data Tag and Comparator One Cache line of Data To Next Lower Level In Hierarchy 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Recall Second Level Cache Proc L2 Equations AMAT Hit TimeL1 Miss RateL1 x Miss PenaltyL1 L1 Cache Miss PenaltyL1 Hit TimeL2 Miss RateL2 x Miss PenaltyL2 L2 Cache AMAT Hit TimeL1 Miss RateL1 x Hit TimeL2 Miss RateL2 x Miss PenaltyL2 Definitions Local miss rate misses in this cache divided by the total number of memory accesses to this cache Miss rateL2 Global miss rate misses in this cache divided by the total number of memory accesses generated by the CPU Miss RateL1 x Miss RateL2 Global Miss Rate is what matters 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Recall Harvard Architecture Proc Unified Cache 1 Unified Cache 2 I Cache 1 Proc D Cache 1 Unified Cache 2 Harvard Architecture Unified Sample Statistics 16KB I D Inst miss rate 0 64 Data miss rate 6 47 32KB unified Aggregate miss rate 1 99 Which is better ignore L2 cache Assume 33 loads store hit time 1 miss time 50 Note data hit has 1 stall for unified cache only one port AMATHarvard 1 1 33 x 1 0 64 x50 0 33 1 33 x 1 6 47 x50 2 05 AMATUnified 1 1 33 x 1 1 99 x50 0 33 1 33 X 1 1 1 99 x50 2 24 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Recall Levels of the Memory Hierarchy Capacity Access Time Cost Staging Xfer Unit CPU Registers 100s Bytes 10s ns Registers Cache K Bytes 10 100 ns 01 001 bit Cache Instr Operands Blocks Main Memory M Bytes 100ns 1us 01 001 Memory Disk G Bytes ms 4 3 10 10 cents Disk Tape infinite sec min 10 6 4 28 03 Upper Level faster prog compiler 1 8 bytes cache cntl 8 128 bytes Pages OS 512 4K bytes Files user operator Mbytes Tape UCB Spring 2003 Larger Lower Level CS152 Kubiatowicz What is virtual memory Virtual Physical Address Space Address Space Virtual Address 10 offset V page no Page Table Base Reg index into page table Page Table V Access Rights PA table located in physical P page no memory offset 10 Physical Address Virtual memory treat memory as a cache for the disk Terminology blocks in this cache are called Pages Typical size of a page 1K 8K Page table maps virtual page numbers to physical frames PTE Page Table Entry 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Three Advantages of Virtual Memory Translation Program can be given consistent view of memory even though physical memory is scrambled Makes multithreading reasonable now used a lot Only the most important part of program Working Set must be in physical memory Contiguous structures like stacks use only as much physical memory as necessary yet still grow later Protection Different threads or processes protected from each other Different pages can be given special behavior Read Only Invisible to user programs etc Kernel data protected from User programs Very important for protection from malicious programs Far more viruses under Microsoft Windows Sharing Can map same physical page to multiple users Shared memory 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Issues in Virtual Memory System Design What is the size of information blocks that are transferred from secondary to main storage M page size Contrast with physical block size on disk I e sector size Which region of M is to hold the new block placement policy How do we find a page when we look for it block identification Block of information brought into M and M is full then some region of M must be released to make room for the new block replacement policy What do we do on a write write policy Missing item fetched from secondary memory only on the occurrence of a fault demand load policy cache mem disk reg frame 4 28 03 UCB Spring 2003 pages CS152 Kubiatowicz How big is the translation page table Virtual Page Number Page Offset Simplest way to implement fully associative lookup policy is with large lookup table Each entry in table is some number of bytes say 4 With 4K pages 32 bit address space need 232 4K 220 1 Meg entries x 4 bytes 4MB With 4K pages 64 bit address space need 264 4K 252 entries BIG Can t keep whole page table in memory 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Large Address Spaces Two level Page Tables 1K PTEs 32 bit address 10 P1 index 10 P2 index 4KB 12 page offest 4 bytes 2 GB virtual address space 4 MB of PTE2 paged holes 4 KB of PTE1 4 bytes What about a 48 64 bit address space 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Inverted Page Tables IBM System 38 AS400 implements 64 bit addresses 48 bits translated start of object contains a 12 bit tag Virtual Page hash V Page P Frame TLBs or virtually addressed caches are critical 4 28 03 UCB Spring 2003 CS152 Kubiatowicz Virtual Address and a Cache Step backward VA CPU miss PA Translation Cache Main Memory hit data Virtual memory seems to be really slow Must access memory on load store even cache hits Worse if translation not completely in memory may
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