CS152 Computer Architecture and Engineering Lecture 23 Virtual Memory Buses and I/O #1Recall: Cache PerformanceRecall: Cache techniquesRecall: Reducing Misses via a “Victim Cache”Recall: Second-Level CacheRecall: Harvard ArchitectureRecall: Levels of the Memory HierarchyWhat is virtual memory?Three Advantages of Virtual MemoryIssues in Virtual Memory System DesignHow big is the translation (page) table?Large Address SpacesInverted Page TablesVirtual Address and a Cache: Step backward???Making address translation practical: TLBTLB organization: include protectionExample: R3000 pipeline includes TLB stagesAdministriviaAdministrivia II: Final project optionsWhat is the replacement policy for TLBs?Page Replacement: Not Recently Used (1-bit LRU, Clock)Slide 22Reducing translation time furtherOverlapped TLB & Cache AccessProblems With Overlapped TLB AccessAnother option: Virtually Addressed CacheCache Optimization: Alpha 21064What is a bus?BusesAdvantages of BusesDisadvantage of BusesThe General Organization of a BusMaster versus SlaveTypes of BusesA Computer System with One Bus: Backplane BusA Two-Bus SystemA Three-Bus System (+ backside cache)Main components of Intel Chipset: Pentium II/IIIWhat is DMA (Direct Memory Access)?What defines a bus?Summary #1 / 2: Virtual MemorySummary #2 / 24/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.1CS152Computer Architecture and EngineeringLecture 23Virtual MemoryBuses and I/O #1April 28, 2003John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.2Execution_Time = Instruction_Count x Cycle_Time x (ideal CPI + Memory_Stalls/Inst + Other_Stalls/Inst)Memory_Stalls/Inst = Instruction Miss Rate x Instruction Miss Penalty +Loads/Inst x Load Miss Rate x Load Miss Penalty +Stores/Inst x Store Miss Rate x Store Miss PenaltyAverage Memory Access time (AMAT) = Hit TimeL1 + (Miss RateL1 x Miss PenaltyL1) =(Hit RateL1 x Hit TimeL1) + (Miss RateL1 x Miss TimeL1)Average Memory Access time = Hit Time + (Miss Rate x Miss Penalty)Recall: Cache Performance4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.3Recall: Cache techniques°Caches, TLBs, Virtual Memory all understood by examining how they deal with 4 questions: 1) Where can block be placed? 2) How is block found? 3) What block is replaced on miss? 4) How are writes handled?°Techniques people use to improve the miss rate of caches:Technique MR MP HT ComplexityLarger Block Size + – 0Higher Associativity + – 1Victim Caches + 2Pseudo-Associative Caches + 2HW Prefetching of Instr/Data + 2Compiler Controlled Prefetching + 3Compiler Reduce Misses + 04/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.4To Next Lower Level InHierarchyDATATAGSOne Cache line of DataTag and ComparatorOne Cache line of DataTag and ComparatorOne Cache line of DataTag and ComparatorOne Cache line of DataTag and ComparatorRecall: Reducing Misses via a “Victim Cache”°How to combine fast hit time of direct mapped yet still avoid conflict misses? °Add buffer to place data discarded from cache°Jouppi [1990]: 4-entry victim cache removed 20% to 95% of conflicts for a 4 KB direct mapped data cache°Used in Alpha, HP machines4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.5°L2 EquationsAMAT = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2AMAT = Hit TimeL1 + Miss RateL1 x (Hit TimeL2 + Miss RateL2 x Miss PenaltyL2)°Definitions:•Local miss rate— misses in this cache divided by the total number of memory accesses to this cache (Miss rateL2)•Global miss rate—misses in this cache divided by the total number of memory accesses generated by the CPU (Miss RateL1 x Miss RateL2) •Global Miss Rate is what mattersRecall: Second-Level CacheProcL1 CacheL2 Cache4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.6°Sample Statistics:•16KB I&D: Inst miss rate=0.64%, Data miss rate=6.47%•32KB unified: Aggregate miss rate=1.99%°Which is better (ignore L2 cache)?•Assume 33% loads/store, hit time=1, miss time=50•Note: data hit has 1 stall for unified cache (only one port)AMATHarvard=(1/1.33)x(1+0.64%x50)+(0.33/1.33)x(1+6.47%x50) = 2.05AMATUnified=(1/1.33)x(1+1.99%x50)+(0.33/1.33)X(1+1+1.99%x50)= 2.24ProcI-Cache-1ProcUnifiedCache-1UnifiedCache-2D-Cache-1ProcUnifiedCache-2Recall: Harvard ArchitectureUnifiedHarvard Architecture4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.7CPU Registers100s Bytes<10s nsCacheK Bytes10-100 ns$.01-.001/bitMain MemoryM Bytes100ns-1us$.01-.001DiskG Bytesms10 - 10 cents-3-4CapacityAccess TimeCostTapeinfinitesec-min10-6RegistersCacheMemoryDiskTapeInstr. OperandsBlocksPagesFilesStagingXfer Unitprog./compiler1-8 bytescache cntl8-128 bytesOS512-4K bytesuser/operatorMbytesUpper LevelLower LevelfasterLargerRecall: Levels of the Memory Hierarchy4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.8°Virtual memory => treat memory as a cache for the disk°Terminology: blocks in this cache are called “Pages”•Typical size of a page: 1K — 8K°Page table maps virtual page numbers to physical frames•“PTE” = Page Table EntryPhysical Address SpaceVirtual Address SpaceWhat is virtual memory?Virtual AddressPage TableindexintopagetablePage TableBase RegVAccessRightsPAV page no. offset10table locatedin physicalmemoryP page no. offset10Physical Address4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.9Three Advantages of Virtual Memory°Translation: •Program can be given consistent view of memory, even though physical memory is scrambled•Makes multithreading reasonable (now used a lot!)•Only the most important part of program (“Working Set”) must be in physical memory.•Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later.°Protection:•Different threads (or processes) protected from each other.•Different pages can be given special behavior- (Read Only, Invisible to user programs, etc).•Kernel data protected from User programs•Very important for protection from malicious programs=> Far more “viruses” under Microsoft Windows°Sharing:•Can map same physical page to multiple users(“Shared memory”)4/28/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec23.10What is the size of information blocks that are transferred from secondary to main storage (M)? page size(Contrast with physical block size on disk, I.e. sector size)Which region of M is
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