CS152 Computer Architecture and Engineering Lecture 1 Introduction and Five Components of a Computer January 20 1999 John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Overvie w Intro to Computer Architecture 30 minutes Administrative Matters 5 minutes Course Style Philosophy and Structure 15 min Break 5 min Organization and Anatomy of a Computer 25 min 1 20 99 UCB Spring 1999 CS152 Kubiatowicz What is Computer Architecture Computer Architecture Instruction Set Architecture Machine Organization 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Instruction Set Architecture subset of Computer Arch the attributes of a computing system as seen by the programmer i e the conceptual structure and functional behavior as distinct from the organization of the data flows and controls the logic design and the physical implementation Amdahl Blaaw and Brooks 1964 SOFTWARE Organization of Programmable Storage Data Types Data Structures Encodings Representations Instruction Set Instruction Formats Modes of Addressing and Accessing Data Items and Instructions Exceptional Conditions 1 20 99 UCB Spring 1999 CS152 Kubiatowicz The Instruction Set a Critical Interface software instruction set hardware 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Example ISAs Instruction Set Architectures Digital Alpha v1 v3 1992 97 HP PA RISC v1 1 v2 0 1986 96 Sun Sparc v8 v9 1987 95 SGI MIPS MIPS I II III IV V 1986 96 Intel 8086 80286 80386 80486 Pentium MMX 1978 96 1 20 99 UCB Spring 1999 CS152 Kubiatowicz MIPS R3000 Instruction Set Architecture Summary Registers Instruction Categories Load Store Computational Jump and Branch Floating Point coprocessor Memory Management Special R0 R31 PC HI LO 3 Instruction Formats all 32 bits wide OP rs rt OP rs rt OP 1 20 99 rd sa funct immediate jump target UCB Spring 1999 Q How many already familiar with MIPS ISA CS152 Kubiatowicz Organizatio n Capabilities Performance Characteristics of Principal Functional Units e g Registers ALU Shifters Logic Units Logic Designer s View ISA Level FUs Interconnect Ways in which these components are interconnected Information flows between components Logic and means by which such information flow is controlled Choreography of FUs to realize the ISA Register Transfer Level RTL Description 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Example Organization TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 MBus Module SuperSPARC Floating point Unit L2 Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface 1 20 99 CC MBus L64852 MBus control M S Adapter SBus SBus DMA SBus Cards UCB Spring 1999 SCSI Ethernet DRAM Controller STDIO serial kbd mouse audio RTC Boot PROM Floppy CS152 Kubiatowicz What is Computer Architecture Application Operating System Compiler Firmware Instr Set Proc I O system Instruction Set Architecture Datapath Control Digital Design Circuit Design Layout Coordination of many levels of abstraction Under a rapidly changing set of forces Design Measurement and Evaluation 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Forces on Computer Architecture Technology Programming Languages Applications Computer Architecture Operating Systems 1 20 99 Cleverness History UCB Spring 1999 CS152 Kubiatowicz Technology DRAM chip capacity 100000000 Microprocessor Logic Density DRAM Size 1980 64 Kb 1983 256 Kb 1986 1 Mb 1989 4 Mb 1992 16 Mb 1996 64 Mb 1999 256 Mb 2002 1 Gb 10000000 R10000 Pentium R4400 i80486 1000000 Transistors Year i80386 i80286 100000 R3010 i8086 SU MIPS i80x86 M68K MIP S Alpha 10000 i4004 1000 1970 1975 1980 1985 1990 1995 2000 2005 In 1985 the single chip processor 32 bit and the single board computer emerged workstations personal computers multiprocessors have been riding this wave since In the 2002 timeframe these may well look like mainframes compared single chip computerCS152 Kubiatowicz 1 20 99 maybe 2 chips UCB Spring 1999 Technology dramatic change Processor logic capacity about 30 per year clock rate about 20 per year Memory DRAM capacity about 60 per year 4x every 3 years Memory speed about 10 per year Cost per bit improves about 25 per year Disk capacity about 60 per year 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Performance Trends Log of Performance Supercomputers Mainframes Minicomputers Microprocessors Year 1970 1 20 99 1975 1980 1985 UCB Spring 1999 1990 1995 CS152 Kubiatowicz Processor Performance SPEC performance now improves 50 per year 2x every 1 5 years 300 250 Performance RISC 200 150 Intel x86 RISC introduction 100 50 35 yr 1995 1994 1993 1992 1991 1990 1989 1988 1987 1986 1985 1984 1983 1982 0 Year Did RISC win the technology battle and lose the market war CS152 Kubiatowicz 1 20 99 UCB Spring 1999 Applications and Languages CAD CAM CAE Lotus DOS Multimedia The Web JAVA 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Measurement and Evaluation Design Architecture is an iterative process searching the space of possible designs at all levels of computer systems Analysis Creativity Cost Performance Analysis Good Ideas Bad Ideas 1 20 99 Mediocre Ideas UCB Spring 1999 CS152 Kubiatowicz Why do Computer Architecture CHANGE It s exciting It has never been more exciting It impacts every other aspect of electrical engineering and computer science 1 20 99 UCB Spring 1999 CS152 Kubiatowicz CS152 Course Content Computer Architecture and Engineering Instruction Set Design Computer Organization Interfaces Hardware Components Compiler System View Logic Designer s View Building Architect Construction Engineer 1 20 99 UCB Spring 1999 CS152 Kubiatowicz CS152 So what s in it for me In depth understanding of the inner workings of modern computers their evolution and trade offs present at the hardware software boundary Insight into fast slow operations that are easy hard to implementation hardware Experience with the design process in the context of a large complex hardware design Functional Spec Control Datapath Physical implementation Modern CAD tools Designer s Conceptual toolbox 1 20 99 UCB Spring 1999 CS152 Kubiatowicz Conceptual tool box Evaluation Techniques Levels of translation e g Compilation Levels of Interpretation e g Microprogramming Hierarchy e g registers cache mem disk tape Pipelining and Parallelism Static Dynamic Scheduling Indirection and Address Translation Synchronous and Asynchronous Control Transfer Timing Clocking and Latching CAD Programs Hardware Description Languages Simulation Physical Building Blocks e g CLA Understanding
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