CS 152 Computer Architecture and Engineering Lecture 2 Simple Machine Implementations Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 January 21 2010 CS152 Spring 2010 Last Time in Lecture 1 Computer Science at crossroads from sequential to parallel computing Computer Architecture ISAs and RTL CS152 is about interaction of hardware and software and design of appropriate abstraction layers Comp Arch shaped by technology and applications History provides lessons for the future Cost of software development a large constraint on architecture Compatibility a key solution to software cost IBM 360 introduces notion of family of machines running same ISA but very different implementations Six different machines released on same day April 7 1964 Future proofing for subsequent generations of machine January 21 2010 CS152 Spring 2010 2 Instruction Set Architecture ISA The contract between software and hardware Typically described by giving all the programmervisible state registers memory plus the semantics of the instructions that operate on that state IBM 360 was first line of machines to separate ISA from implementation aka microarchitecture Many implementations possible for a given ISA E g today you can buy AMD or Intel processors that run the x8664 ISA E g 2 many cellphones use the ARM ISA with implementations from many different companies including TI Qualcomm Samsung Marvell etc E g 3 the Soviets build code compatible clones of the IBM360 as did Amdhal after he left IBM January 21 2010 CS152 Spring 2010 3 Microprogramming Today a brief look at microprogrammed machines To show how to build very small processors with complex ISAs To help you understand where CISC machines came from Because it is still used in the most common machines x86 PowerPC IBM360 As a gentle introduction into machine structures To help understand how technology drove the move to RISC CISC RISC names came much later than the style of machines they refer to January 21 2010 CS152 Spring 2010 4 ISA to Microarchitecture Mapping ISA often designed with particular microarchitectural style in mind e g CISC microcoded RISC hardwired pipelined VLIW fixed latency in order parallel pipelines JVM software interpretation But can be implemented with any microarchitectural style Intel Nehalem hardwired pipelined CISC x86 machine with some microcode support Simics Software interpreted SPARC RISC machine Intel could implement a dynamically scheduled outof order VLIW Itanium IA 64 processor ARM Jazelle A hardware JVM processor This lecture a microcoded RISC MIPS machine January 21 2010 CS152 Spring 2010 5 Microarchitecture Implementation of an ISA status lines Controller control points Data path Structure How components are connected Static Behavior How data moves between components Dynamic January 21 2010 CS152 Spring 2010 6 Microcontrol Unit Maurice Wilkes 1954 op conditional code flip flop First used in EDSAC 2 completed 1958 Next state address Matrix A Matrix B Embed the control logic state table in a memory array Decoder Memory Control lines to ALU MUXs Registers January 21 2010 CS152 Spring 2010 7 Microcoded Microarchitecture busy zero opcode holds fixed microcode instructions mcontroller ROM Datapath Data holds user program written in macrocode instructions e g MIPS x86 etc January 21 2010 Addr Memory RAM CS152 Spring 2010 enMem MemWrt 8 The MIPS32 ISA Processor State 32 32 bit GPRs R0 always contains a 0 16 double precision 32 single precision FPRs FP status register used for FP compares exceptions PC the program counter See H P some other special registers Appendix B for full description Data types 8 bit byte 16 bit half word 32 bit word for integers 32 bit word for single precision floating point 64 bit word for double precision floating point Load Store style instruction set data addressing modes immediate indexed branch addressing modes PC relative register indirect Byte addressable memory big endian mode All instructions are 32 bits January 21 2010 CS152 Spring 2010 9 MIPS Instruction Formats 6 0 ALU ALUi Mem 5 5 rs rt opcode rs rt 6 55 opcode rs rt 6 5 5 opcode rs 5 rd January 21 2010 6 func immediate 16 displacement rd rs func rt rt rs op immediate M rs displacement 16 offset 6 5 5 opcode rs 6 opcode 5 0 BEQZ BNEZ 16 JR JALR 26 offset CS152 Spring 2010 J JAL 10 Data Formats and Memory Addresses Data formats Bytes Half words words and double words Some issues Byte addressing Big Endian vs Little Endian Most Significant Byte 0 1 3 2 2 3 1 Least Significant Byte 0 Byte Addresses Word alignment Suppose the memory is organized in 32 bit words Can a word address begin only at 0 4 8 0 January 21 2010 1 2 3 4 CS152 Spring 2010 5 6 7 11 A Bus based Datapath for MIPS Opcode ldIR zero OpSel ldA busy 32 PC 31 Link rd rt rs ldB 2 rd rt rs IR ExtSel Imm Ext 2 3 A ALU control enImm 32 GPRs PC 32 bit Reg enALU RegWrt Memory MemWrt enReg data Bus MA addr addr B ALU RegSel ldMA data enMem 32 Microinstruction register to register transfer 17 control signals MA B PC means RegSel PC enReg yes Reg rt means RegSel rt enReg yes January 21 2010 CS152 Spring 2010 ldMA yes ldB yes 12 Memory Module addr busy RAM din we Write 1 Read 0 Enable dout bus Assumption Memory operates independently and is slow as compared to Reg to Reg transfers multiple CPU clock cycles per access January 21 2010 CS152 Spring 2010 13 Instruction Execution Execution of a MIPS instruction involves 1 2 3 4 5 January 21 2010 instruction fetch decode and register fetch ALU operation memory operation optional write back to register file optional the computation of the next instruction address CS152 Spring 2010 14 Microprogram Fragments instr fetch MA PC A PC IR Memory PC A 4 dispatch on OPcode ALU ALUi January 21 2010 can be treated as a macro A Reg rs B Reg rt Reg rd func A B do instruction fetch A Reg rs B Imm sign extension Reg rt Opcode A B do instruction fetch CS152 Spring 2010 15 Microprogram Fragments cont LW A Reg rs B Imm MA A B Reg rt Memory do instruction fetch J A PC B IR PC JumpTarg A B do instruction fetch beqz January 21 2010 JumpTarg A B A 31 28 B 25 0 00 A Reg rs If zero A then go to bz taken do instruction fetch bz taken A PC B Imm 2 PC A B do instruction fetch CS152 Spring 2010 16 MIPS Microcontroller first attempt Opcode zero Busy memory 6 PC state s addr ROM size 2 opcode status s words Word size control s bits How big is s s Program ROM
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