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Berkeley COMPSCI 152 - Simple Machine Implementations

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Slide 1Last Time in Lecture 1Instruction Set Architecture (ISA)MicroprogrammingISA to Microarchitecture MappingMicroarchitecture: Implementation of an ISAMicrocontrol Unit Maurice Wilkes, 1954Microcoded MicroarchitectureThe MIPS32 ISAMIPS Instruction FormatsData Formats and Memory AddressesA Bus-based Datapath for MIPSMemory ModuleInstruction ExecutionMicroprogram FragmentsMicroprogram Fragments (cont.)MIPS Microcontroller: first attemptMicroprogram in the ROM worksheetMicroprogram in the ROMMicroprogram in the ROM Cont.Size of Control StoreReducing Control Store SizeCS152 AdministriviaCollaboration PolicyMIPS Controller V2Jump LogicInstruction Fetch & ALU:MIPS-Controller-2Load & Store: MIPS-Controller-2Branches: MIPS-Controller-2Jumps: MIPS-Controller-2VAX 11-780 MicrocodeImplementing Complex InstructionsMem-Mem ALU Instructions: MIPS-Controller-2Performance IssuesHorizontal vs Vertical mCodeNanocodingMicroprogramming in IBM 360IBM Card Capacitor Read-Only StorageMicrocode EmulationMicroprogramming thrived in the SeventiesWritable Control Store (WCS)Microprogramming: early EightiesModern UsageAcknowledgementsJanuary 21, 2010 CS152 Spring 2010CS 152 Computer Architecture and Engineering Lecture 2 - Simple Machine ImplementationsKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152January 21, 2010 CS152 Spring 20102Last Time in Lecture 1•Computer Science at crossroads from sequential to parallel computing•Computer Architecture >> ISAs and RTL–CS152 is about interaction of hardware and software, and design of appropriate abstraction layers•Comp. Arch. shaped by technology and applications–History provides lessons for the future•Cost of software development a large constraint on architecture–Compatibility a key solution to software cost•IBM 360 introduces notion of “family of machines” running same ISA but very different implementations–Six different machines released on same day (April 7, 1964)–“Future-proofing” for subsequent generations of machineJanuary 21, 2010 CS152 Spring 2010Instruction Set Architecture (ISA)•The contract between software and hardware•Typically described by giving all the programmer-visible state (registers + memory) plus the semantics of the instructions that operate on that state•IBM 360 was first line of machines to separate ISA from implementation (aka. microarchitecture)•Many implementations possible for a given ISA–E.g., today you can buy AMD or Intel processors that run the x86-64 ISA.–E.g.2: many cellphones use the ARM ISA with implementations from many different companies including TI, Qualcomm, Samsung, Marvell, etc.–E.g.3., the Soviets build code-compatible clones of the IBM360, as did Amdhal after he left IBM.3January 21, 2010 CS152 Spring 20104Microprogramming•Today, a brief look at microprogrammed machines–To show how to build very small processors with complex ISAs–To help you understand where CISC* machines came from–Because it is still used in the most common machines (x86, PowerPC, IBM360)–As a gentle introduction into machine structures–To help understand how technology drove the move to RISC** CISC/RISC names came much later than the style of machines they refer to.January 21, 2010 CS152 Spring 20105ISA to Microarchitecture Mapping•ISA often designed with particular microarchitectural style in mind, e.g.,–CISC  microcoded–RISC  hardwired, pipelined–VLIW  fixed-latency in-order parallel pipelines–JVM  software interpretation•But can be implemented with any microarchitectural style–Intel Nehalem: hardwired pipelined CISC (x86) machine (with some microcode support)–Simics: Software-interpreted SPARC RISC machine–Intel could implement a dynamically scheduled out-of-order VLIW Itanium (IA-64) processor–ARM Jazelle: A hardware JVM processor–This lecture: a microcoded RISC (MIPS) machineJanuary 21, 2010 CS152 Spring 20106Microarchitecture: Implementation of an ISAStructure: How components are connected. StaticBehavior: How data moves between components DynamicControllerDatapathcontrolpointsstatuslinesJanuary 21, 2010 CS152 Spring 20107Microcontrol Unit Maurice Wilkes, 1954 Embed the control logic state table in a memory arrayMatrix AMatrix BDecoderNext stateop conditionalcode flip-flop addressControl lines toALU, MUXs, RegistersFirst used in EDSAC-2, completed 1958MemoryJanuary 21, 2010 CS152 Spring 20108Microcoded MicroarchitectureMemory(RAM)Datapathmcontroller(ROM)AddrDatazero?busy?opcodeenMemMemWrtholds fixedmicrocode instructions holds user program written in macrocode instructions (e.g., MIPS, x86, etc.)January 21, 2010 CS152 Spring 20109The MIPS32 ISA• Processor State32 32-bit GPRs, R0 always contains a 016 double-precision/32 single-precision FPRsFP status register, used for FP compares & exceptionsPC, the program countersome other special registers• Data types8-bit byte, 16-bit half word 32-bit word for integers32-bit word for single precision floating point64-bit word for double precision floating point• Load/Store style instruction setdata addressing modes- immediate & indexedbranch addressing modes- PC relative & register indirectByte addressable memory- big-endian modeAll instructions are 32 bitsSee H&P Appendix B for full descriptionJanuary 21, 2010 CS152 Spring 201010MIPS Instruction Formats 6 5 5 16opcode rs offset BEQZ, BNEZ 6 26opcode offset J, JAL 6 5 5 16opcode rs JR, JALRopcode rsrt immediate rt  (rs) op immediate 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt)ALUALUi 6 55 16opcode rs rt displacement M[(rs) + displacement]MemJanuary 21, 2010 CS152 Spring 201011Data formats: Bytes, Half words, words and double wordsSome issues• Byte addressing Big Endian 0 1 2 3 vs. Little Endian 3 2 1 0• Word alignment Suppose the memory is organized in 32-bit words.Can a word address begin only at 0, 4, 8, .... ?Data Formats and Memory Addresses 0 1 2 3 4 5 6 7 Most Significant ByteLeast Significant ByteByte AddressesJanuary 21, 2010 CS152 Spring 201012A Bus-based Datapath for MIPSMicroinstruction: register to register transfer (17 control signals) MA  PC means RegSel = PC;


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Berkeley COMPSCI 152 - Simple Machine Implementations

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