CS152 Computer Architecture and Engineering Lecture 15 Virtual Memory 2004 10 21 Dave Patterson www cs berkeley edu patterson John Lazzaro www cs berkeley edu lazzaro www inst eecs berkeley edu cs152 CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 1 Last Time How to Design a Cache Most design errors come from incorrect specification of state machine behavior Common bugs stalls block replacement write buffer State Machine To CPU Control Control Control Addr To CPU Din Dout CS 152 L15 Virtual Memory Addr Blocks Tags Din Dout To Lower Level Memory To Lower Level Memory UC Regents Fall 2004 UCB 2 Today s Lecture Virtual Memory DRAM technology Virtual address spaces Page table layout TLB design options CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 3 DRAM Technology CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 4 Why DRAM over SRAM Density 01 bit SRAM Cell Large 1 234 6 transistors nFET and pFET 1 3 interface wires 1 Transistor Memory Cell DRAM Vdd and Gnd 0 Write DRAM Cell Small 1 bit 8 9 0 word 0 0 row select 5 6 7 8 9 0 6 7 2 Select row transistor capacitor 1 A 9 Read nFET only 1 Drive bit line 1 1 1 1 Precharge bit line to wires Vdd 2 2 interface 1 2 9 77 bit no Vdd 3 Cell and bit line share charges 1 2 09 9 B 7 0 A advantage 3X to on 10X depends Density Very small voltage changes the bit line on metric 0 6 0 8 6 7 CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 2 Select row 4 Sense fancy sense amp Can detect changes of 1 million electrons 1 1 5 T 012 3 1 Transistor Memory Cell DRAM DRAM Reading Writing Refresh 1 Writing DRAM Write Drive data on bit line 1 Drive bit line Select row row select 1 1 2 Select row Capacitor holds state Read 1 1 Precharge bit line Vdd 2 for 60 ms to then 1 Transistor Memory Cell DRAM 2 Select row must do refresh bit 3 Cell and bit line share charges Very small voltage changes To learn more DRAM Circuit 4 Sense fancy sense amp Design A Tutorial Write Reading DRAM Brent Keeth Can 1 Drive bitdetect line R Jacob Baker ISBN 0 7803 6014 1 5 2 Write Selectrestore row November 2000 Wiley IEEE Press on the bit line UCB Spring 2004 3 Cell and bit line share charges Refresh a dummy read 1 1 bit 1 Very small voltage changes on the bit line CS 152 L15 Virtual Memory 4 Sense fancy sense amp 1 changes of 1 million electrons Selectthe row value RefreshSense bit line Read million electrons 1 1 do a dummy to every cell 1 Just Precharge bit line read to Vdd 2 value back 2 Write Select row 4 12 04 row select Can detect changes of 1 million electrons CS152 Kubiatowicz Lec19 21 UC Regents Fall 2004 UCB 6 if a READ command is registered at T0 and the latency is programmed to two clocks the DQs will start driving after T1 and the data will be valid by T2 as shown in Figure 2 Table 2DRAM below indicates the operating frequenSynchronous SDRAM Interface cies at which each CAS latency setting can be used A clocked bus states should Note not Thisbeexample is best case Reserved used as unknown opprotocol For a random access DRAM takes eration or incompatibility with future versions mayMHz result ex 100 many more than 2 cycles T0 T1 T2 NOP NOP M0 M9 RE no T3 CLK COMMAND READ tLZ S tOH DOUT DQ tAC Cache controller puts commands on bus CLK CS 152 L15 Virtual Memory CAS Latency 2 CAS Column Address Strobe T0 T1 T2 Data comes out several cycles T3 later T4 From Micron 128 Mb SDRAM data sheet on resources web page UC Regents Fall 2004 UCB 7 COMMAND READ NOP NOP NOP Administrivia Lab 3 HW 3 Lab 4 Lab 3 final demo on 10 22 Friday Lab 4 to be posted on 10 22 Friday if all goes well Lab 3 report due Monday 10 25 11 59 PM Homework 3 due 10 26 Tuesday 283 Soda in CS 152 box at 5 PM CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 8 Virtual Addressing CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 9 The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU A0 A31 Where we are in CS 152 D0 D31 Memory D0 D31 Data All programs share one address space The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 10 Solution Add a Layer of Indirection Physical Addresses Virtual Addresses A0 A31 Virtual Physical Address Translation CPU D0 D31 A0 A31 Memory D0 D31 Data User programs run in an standardized virtual address space Address Translation hardware managed by the operating system OS maps virtual address to physical memory Hardware supports modern OS features Protection Translation Sharing CS 152 L15 Virtual Memory UC Regents Fall 2004 UCB 11 MIPS R4000 Address Space Model Process A ASID 12 32 2 1 Address Error 2 ASID Address Space Identifier Process A and B have independent address spaces 2 GB 0 ASID 13 32 2 1 All address spaces translated to standard map May only be accessed by kernel supervisor 31 Process B Address Error 2 31 When Process A writes its address 9 it writes to a different physical memory location than Process B s address 9 To let Process A and B share memory OS maps parts of ASID 12 and ASID 13 to the same physical memory locations 2 GB 0 Still works slowly if a process accesses more virtual memory than CS 152 L15 Virtual Memory the machine has physical memory UC Regents Fall 2004 UCB 12 Chapter 4 4 3 System Control Coprocessor The System Control Cop rocessor CP0 is im p lem ented as an integral p art of the CPU and su p p orts m em ory m anagem ent ad d ress translation excep tion hand ling and other p rivileged op erations CP0 contains the registers show n in Figu re 4 7 p lu s a 48 entry TLB The sections that follow d escribe how the p rocessor u ses the m em ory m anagem ent related registers MIPS R4000 Who s Running on the CPU System Control Registers Each CP0 register has a u niqu e nu m ber that id entifies it this nu m ber is referred to as the register number For instance the Page M ask register is register nu m ber 5 EntryLo0 EntryLo0 2 2 EntryHi EntryHi 10 EntryLo1 3 47 Context Index 4 Random Random Count Page Mask Page Mask Status 12 13 Wired Wired EPC WatchLo 1 6 0 LLAddr 17 19 Config ECC 16 26 TagHi 28 29 Cause Status 12 …
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