CS 152 L15 Virtual Memory () UC Regents Fall 2004 © UCB2004-10-21 Dave Patterson(www.cs.berkeley.edu/~patterson)John Lazzaro (www.cs.berkeley.edu/~lazzaro)www-inst.eecs.berkeley.edu/~cs152/CS152 – Computer Architecture andEngineeringLecture 15 – Virtual Memory1CS 152 L15 Virtual Memory () UC Regents Fall 2004 © UCB Last Time: How to Design a CacheToCPUToLowerLevelMemoryToCPUToLowerLevelMemoryTagsBlocksAddrDinDoutAddrDinDoutState MachineControlControlControlMost design errors come from incorrect specification of state machine behavior!Common bugs: stalls, block replacement, write buffer2CS 152 L15 Virtual Memory () UC Regents Fall 2004 © UCBToday’s Lecture - Virtual MemoryVirtual address spacesPage table layoutTLB design optionsDRAM technology3UC Regents Fall 2004 © UCBCS 152 L15 Virtual Memory ()DRAM Technology4UC Regents Fall 2004 © UCBCS 152 L15 Virtual Memory ()Why DRAM over SRAM? Density!bit!"#$%&'())* ++,!-.)'/ 012-3/414-56&1'--!"#$%&#'()'*"+,(-"*.$+&/"0(1234)(-'##1 5$+6'+(7'##(! #"8'+(9'0/&%,:(;&6;'+(7"/%<=&%((((((((((((((((((1 >"(+'?+'/;(+'@A&+'9(1 2&*.#'(+'$9(! ?$/%'+($77'//(1 2%$09$+9(B-(.+"7'//(! 0$%A+$#(?"+(&0%'6+$%&"0(8&%;(#"6&71 C34)(-'##1 2*$##'+(7'##(! ;&6;'+(9'0/&%,:(#"8'+(7"/%<=&%(1 >''9/(.'+&"9&7(+'?+'/;:($09(+'?+'/;($?%'+(+'$9(1 -"*.#'D(+'$9(! #"06'+($77'//(%&*'(1 2.'7&$#(B-(.+"7'//(! 9&??&7A#%(%"(&0%'6+$%'(8&%;(#"6&7(7&+7A&%/8"+9(#&0'=&%(#&0'=&%(#&0'8"+9(#&0'=&%(#&0'!"#$%&'()&*$+',,#&#-.#$/#01##-$+',,#&#-0$(#(2&*$0*%#3$'3$0"#$/'0 .#445bitword10SRAM Cell: Large6 transistorsnFET and pFET3 interface wiresVdd and GndDRAM Cell: Smalltransistor + capacitornFET only2 interface wiresno Vdd4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.211-Transistor Memory Cell (DRAM)° Write:• 1. Drive bit line• 2.. Select row° Read:• 1. Precharge bit line to Vdd/2• 2.. Select row• 3. Cell and bit line share charges- Very small voltage changes on the bit line• 4. Sense (fancy sense amp)- Can detect changes of ~1 million electrons• 5. Write: restore the value ° Refresh• 1. Just do a dummy read to every cell.row selectbit4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.22DRAM Capacitors: more capacitance in a small area° Trench capacitors:• Logic ABOVE capacitor• Gain in surface area of capacitor• Better Scaling properties• Better Planarization° Stacked capacitors• Logic BELOW capacitor• Gain in surface area of capacitor• 2-dim cross-section quite small4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.23Classical DRAM Organization (square)rowdecoderrowaddressColumn Selector &I/O CircuitsColumnAddressdataRAM CellArrayword (row) selectbit (data) lines° Row and Column Address together: • Select 1 bit a timeEach intersection representsa 1-T DRAM Cell4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.24DRAM logical organization (4 Mbit)° Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage CellDensity advantage: 3X to 10X, depends on metric5UC Regents Fall 2004 © UCBCS 152 L15 Virtual Memory ()DRAM: Reading, Writing, RefreshWriting DRAM:Drive data on bit lineSelect row4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.211-Transistor Memory Cell (DRAM)° Write:• 1. Drive bit line• 2.. Select row° Read:• 1. Precharge bit line to Vdd/2• 2.. Select row• 3. Cell and bit line share charges- Very small voltage changes on the bit line• 4. Sense (fancy sense amp)- Can detect changes of ~1 million electrons• 5. Write: restore the value ° Refresh• 1. Just do a dummy read to every cell.row selectbit4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.22DRAM Capacitors: more capacitance in a small area° Trench capacitors:• Logic ABOVE capacitor• Gain in surface area of capacitor• Better Scaling properties• Better Planarization° Stacked capacitors• Logic BELOW capacitor• Gain in surface area of capacitor• 2-dim cross-section quite small4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.23Classical DRAM Organization (square)rowdecoderrowaddressColumn Selector &I/O CircuitsColumnAddressdataRAM CellArrayword (row) selectbit (data) lines° Row and Column Address together: • Select 1 bit a timeEach intersection representsa 1-T DRAM Cell4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.24DRAM logical organization (4 Mbit)° Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage Cell111Reading DRAMSelect rowSense bit line(~1 million electrons)Write value back4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.211-Transistor Memory Cell (DRAM)° Write:• 1. Drive bit line• 2.. Select row° Read:• 1. Precharge bit line to Vdd/2• 2.. Select row• 3. Cell and bit line share charges- Very small voltage changes on the bit line• 4. Sense (fancy sense amp)- Can detect changes of ~1 million electrons• 5. Write: restore the value ° Refresh• 1. Just do a dummy read to every cell.row selectbit4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.22DRAM Capacitors: more capacitance in a small area° Trench capacitors:• Logic ABOVE capacitor• Gain in surface area of capacitor• Better Scaling properties• Better Planarization° Stacked capacitors• Logic BELOW capacitor• Gain in surface area of capacitor• 2-dim cross-section quite small4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.23Classical DRAM Organization (square)rowdecoderrowaddressColumn Selector &I/O CircuitsColumnAddressdataRAM CellArrayword (row) selectbit (data) lines° Row and Column Address together: • Select 1 bit a timeEach intersection representsa 1-T DRAM Cell4/12/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec19.24DRAM logical organization (4 Mbit)° Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage Cell11111Refresh: a dummy readCapacitor holds statefor 60 ms -- then must do “refresh”To learn more ...DRAM Circuit Design: A TutorialBrent Keeth, R. Jacob BakerISBN: 0-7803-6014-1November 2000,Wiley-IEEE Press6UC Regents Fall 2004 © UCBCS 152 L15 Virtual Memory ()Synchronous DRAM (SDRAM) Interface11128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.128Mb: x4, x8, x16SDRAMOperating ModeThe normal operating mode is selected by setting M7and M8 to zero; the
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