DOC PREVIEW
Berkeley COMPSCI 152 - Lecture 22 – Graphics Processors

This preview shows page 1-2-3-19-20-38-39-40 out of 40 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 40 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

UC Regents Fall 2006 © UCBCS 152 L22: Graphics Processors2006-11-14John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 22 – Graphics Processorswww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue Sun 1UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsToday: Graphics ProcessorsComputer Graphics. A brief introduction to “the pipeline”.Stream Processing. Casting the graphics pipeline into hardware.Unified Pipelines. GeForce 8800,the new architecture from Nvidia.2CS 152 L20: Buses, Disks, and RAID UC Regents Fall 2006 © UCBFigure 2-1 Block diagram167 MHzMaxBus12 MbpsUSBPCI busBootROMUSB 2.0 port (480 Mbps)USB 2.0 port (480 Mbps)PCI USB 2.0controllerDDR SDRAMDIMM slot32 MBDDR RAMDVI/VGA/composite/S-videooutput portEthernet port10/100 MbpsFireWire 400 portAGP 4Xbus167 MHzMemorybus PMUpower controllerPowerbuttonFanOpticaldriveUltraATA/100busDevice 0Device 1Headphone/audio line-out jackHard diskdriveRadeon9200graphics ICAudiocodecEthernetPHYFireWirePHYPowerPC G4microprocessor(L2 cache: 512K 1:1)AirPort ExtremeI2SI2SI2CBluetoothModem portModem moduleData pumpand DAABuilt-inspeakerIntrepidmemorycontrollerand I/OdevicecontrollerMain ICs and BusesThe architecture of Mac mini is designed around the PowerPC G4 microprocessor and the Intrepidmemory and I/O device controller. The Intrepid occupies the center of the block diagram.The MaxBus connects the PowerPC G4 microprocessor to the Intrepid ASIC. The MaxBus has 64 datalines, 32 address lines, and a bus clock speed of 167 MHz. The Intrepid ASIC has other buses thatconnect with the boot ROM, the hard disk drive, and the optical drive, the power controller IC, thesound IC, the internal modem module, and the optional wireless LAN module.The Intrepid I/O controller has a 32-bit PCI bus with a bus clock speed of 33 MHz.Each of the components listed here is described in one of the following sections.16Block Diagram and Buses2005-04-05 | © 2005 Apple Computer, Inc. All Rights Reserved.C H A P T E R 2ArchitectureATI Radeon 9200: Graphics Processing Unit (GPU).Recall: Mac Mini G4 System DiagramTo DisplayAGP 4X: Hi-Speed Graphics BusDedicated Graphics RAMAverage selling price (ASP) for GPUs: $303UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsAbout 12 MB/frame (24-bit pixels)24 frames/sec: 300 MB/second160025604UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsFigure 2-1 Block diagram167 MHzMaxBus12 MbpsUSBPCI busBootROMUSB 2.0 port (480 Mbps)USB 2.0 port (480 Mbps)PCI USB 2.0controllerDDR SDRAMDIMM slot32 MBDDR RAMDVI/VGA/composite/S-videooutput portEthernet port10/100 MbpsFireWire 400 portAGP 4Xbus167 MHzMemorybus PMUpower controllerPowerbuttonFanOpticaldriveUltraATA/100busDevice 0Device 1Headphone/audio line-out jackHard diskdriveRadeon9200graphics ICAudiocodecEthernetPHYFireWirePHYPowerPC G4microprocessor(L2 cache: 512K 1:1)AirPort ExtremeI2SI2SI2CBluetoothModem portModem moduleData pumpand DAABuilt-inspeakerIntrepidmemorycontrollerand I/OdevicecontrollerMain ICs and BusesThe architecture of Mac mini is designed around the PowerPC G4 microprocessor and the Intrepidmemory and I/O device controller. The Intrepid occupies the center of the block diagram.The MaxBus connects the PowerPC G4 microprocessor to the Intrepid ASIC. The MaxBus has 64 datalines, 32 address lines, and a bus clock speed of 167 MHz. The Intrepid ASIC has other buses thatconnect with the boot ROM, the hard disk drive, and the optical drive, the power controller IC, thesound IC, the internal modem module, and the optional wireless LAN module.The Intrepid I/O controller has a 32-bit PCI bus with a bus clock speed of 33 MHz.Each of the components listed here is described in one of the following sections.16Block Diagram and Buses2005-04-05 | © 2005 Apple Computer, Inc. All Rights Reserved.C H A P T E R 2Architecture12 MB Frame BufferFigure 2-1 Block diagram167 MHzMaxBus12 MbpsUSBPCI busBootROMUSB 2.0 port (480 Mbps)USB 2.0 port (480 Mbps)PCI USB 2.0controllerDDR SDRAMDIMM slot32 MBDDR RAMDVI/VGA/composite/S-videooutput portEthernet port10/100 MbpsFireWire 400 portAGP 4Xbus167 MHzMemorybus PMUpower controllerPowerbuttonFanOpticaldriveUltraATA/100busDevice 0Device 1Headphone/audio line-out jackHard diskdriveRadeon9200graphics ICAudiocodecEthernetPHYFireWirePHYPowerPC G4microprocessor(L2 cache: 512K 1:1)AirPort ExtremeI2SI2SI2CBluetoothModem portModem moduleData pumpand DAABuilt-inspeakerIntrepidmemorycontrollerand I/OdevicecontrollerMain ICs and BusesThe architecture of Mac mini is designed around the PowerPC G4 microprocessor and the Intrepidmemory and I/O device controller. The Intrepid occupies the center of the block diagram.The MaxBus connects the PowerPC G4 microprocessor to the Intrepid ASIC. The MaxBus has 64 datalines, 32 address lines, and a bus clock speed of 167 MHz. The Intrepid ASIC has other buses thatconnect with the boot ROM, the hard disk drive, and the optical drive, the power controller IC, thesound IC, the internal modem module, and the optional wireless LAN module.The Intrepid I/O controller has a 32-bit PCI bus with a bus clock speed of 33 MHz.Each of the components listed here is described in one of the following sections.16Block Diagram and Buses2005-04-05 | © 2005 Apple Computer, Inc. All Rights Reserved.C H A P T E R 2ArchitectureA “dumb” graphics card ...12 MB Frame BufferDVI Formatter D/AControl LogicAGP 4X: 1.1 GB/s. Can handle 24 f/s(300 MB/s) for a 2560x1600 display.Double Buffering:CPU writes “next frame” in one buffer. Control logic sends “this frame” out of other buffer to display.Problem: CPU has to compute a new pixel every 10 ns. 10 clock cycles for a 1 GHz CPU clock.5UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsGraphics AccelerationQ. In a multi-core world, why should we use a special processor for graphics? A. Programmers generally use a certain coding style for graphics. We can design a processor to fit the style. Q. What kind of graphics are we accelerating?A. In 2006, interactive entertainment (3-D games). In the 1990s, 2-D acceleration (fast windowing systems, games like Pac-Man).Next: An intro to 3-D graphics.6UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsThe Triangle ...Simplest closed shape that may be defined by straight edges.With enough triangles, you can make anything.7UC Regents Fall 2006 © UCBCS 152 L22: Graphics ProcessorsA cube whose faces are made up of triangles. This is a 3-D model of


View Full Document

Berkeley COMPSCI 152 - Lecture 22 – Graphics Processors

Documents in this Course
Quiz 5

Quiz 5

9 pages

Memory

Memory

29 pages

Quiz 5

Quiz 5

15 pages

Memory

Memory

29 pages

Memory

Memory

35 pages

Memory

Memory

15 pages

Quiz

Quiz

6 pages

Midterm 1

Midterm 1

20 pages

Quiz

Quiz

12 pages

Memory

Memory

33 pages

Quiz

Quiz

6 pages

Homework

Homework

19 pages

Quiz

Quiz

5 pages

Memory

Memory

15 pages

Load more
Download Lecture 22 – Graphics Processors
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 22 – Graphics Processors and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 22 – Graphics Processors 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?