CS152 Computer Architecture and Engineering Lecture 8 Designing Single Cycle ControlRecap: Summary from last timeRecap: The MIPS Instruction FormatsRecap: The MIPS SubsetRecap: A Single Cycle DatapathThe Big Picture: Where are We Now?Outline of Today’s LectureRTL: The Add InstructionInstruction Fetch Unit at the Beginning of AddThe Single Cycle Datapath during AddInstruction Fetch Unit at the End of AddThe Single Cycle Datapath during Or ImmediateThe Single Cycle Datapath during LoadQuestions and Administrative MattersThe Single Cycle Datapath during StoreSlide 17The Single Cycle Datapath during BranchInstruction Fetch Unit at the End of BranchStep 4: Given Datapath: RTL -> ControlA Summary of Control SignalsA Summary of the Control SignalsThe Concept of Local DecodingThe Encoding of ALUopThe Decoding of the “func” FieldThe Truth Table for ALUctrThe Logic Equation for ALUctr<2>The Logic Equation for ALUctr<1>The Logic Equation for ALUctr<0>The ALU Control BlockStep 5: Logic for each control signalThe “Truth Table” for the Main ControlThe “Truth Table” for RegWritePLA Implementation of the Main ControlA Real MIPS Datapath (CNS T0)Putting it All Together: A Single Cycle ProcessorWorst Case Timing (Load)Drawback of this Single Cycle ProcessorSummaryWhere to get more information?2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.1CS152Computer Architecture and EngineeringLecture 8Designing Single Cycle ControlFeb 22, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.2Recap: Summary from last time°5 steps to design a processor•1. Analyze instruction set => datapath requirements•2. Select set of datapath components & establish clock methodology•3. Assemble datapath meeting the requirements•4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.•5. Assemble the control logic°MIPS makes it easier•Instructions same size•Source registers always in same place•Immediates same size, location•Operations always on registers/immediates°Single cycle datapath => CPI=1, CCT => long2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.3Recap: The MIPS Instruction Formats°All MIPS instructions are 32 bits long. The three instruction formats:•R-type•I-type•J-type°The different fields are:•op: operation of the instruction•rs, rt, rd: the source and destination registers specifier•shamt: shift amount•funct: selects the variant of the operation in the “op” field•address / immediate: address offset or immediate value•target address: target address of the jump instruction op target address026316 bits 26 bitsop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rtimmediate0162126316 bits 16 bits5 bits5 bits2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.4Recap: The MIPS Subset°ADD and subtract•add rd, rs, rt•sub rd, rs, rt°OR Imm:•ori rt, rs, imm16°LOAD and STORE•lw rt, rs, imm16•sw rt, rs, imm16°BRANCH:•beq rs, rt, imm16op rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bits2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.5Recap: A Single Cycle Datapath°We have everything except control signals (underline)•Today’s lecture will show you how to generate the control signals32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.6The Big Picture: Where are We Now? °The Five Classic Components of a Computer°Today’s Topic: Designing the Control for the Single Cycle DatapathControlDatapathMemoryProcessorInputOutput2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.7Outline of Today’s Lecture°Recap and Introduction (10 minutes)°Control for Register-Register & Or Immediate instructions (10 minutes)°Questions and Administrative Matters (5 minutes)°Control signals for Load, Store, Branch, & Jump (15 minutes)°Building a local controller: ALU Control (10 minutes)°Break (5 minutes)°The main controller (20 minutes)°Summary (5 minutes)2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.8RTL: The Add Instruction°add rd, rs, rt•mem[PC] Fetch the instruction from memory•R[rd] <- R[rs] + R[rt] The actual operation•PC <- PC + 4 Calculate the next instruction’s addressop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bits2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.9Instruction Fetch Unit at the Beginning of Add°Fetch the instruction from Instruction memory: Instruction <- mem[PC]•This is the same for all instructionsPC ExtAdrInstMemoryAdderAdderPCClk00Mux4nPC_selimm16Instruction<31:0>2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.10The Single Cycle Datapath during Add32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 1ExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkZeroInstruction<31:0>°R[rd] <- R[rs] + R[rt]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt rd shamt funct061116212631nPC_sel= +42/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.11Instruction Fetch Unit at the End of Add°PC <- PC + 4•This is the same for all instructions except: Branch and JumpAdrInstMemoryAdderAdderPCClk00Mux4nPC_selimm16Instruction<31:0>012/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.12The Single Cycle Datapath during Or Immediate°R[rt] <- R[rs] or ZeroExt[Imm16]op rs rt immediate01621263132ALUctr = ClkbusWRegWr = 3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = ExtenderMuxMux3216imm16ALUSrc = ExtOp = MuxMemtoReg = ClkData InWrEn32AdrDataMemory32MemWr = ALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel =2/22/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec8.14The Single Cycle Datapath during Load32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = 1ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch
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