CS152 Computer Architecture and Engineering Lecture 8 Designing Single Cycle Control Feb 22 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Recap Summary from last time 5 steps to design a processor 1 Analyze instruction set datapath requirements 2 Select set of datapath components establish clock methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic MIPS makes it easier Instructions same size Source registers always in same place Immediates same size location Operations always on registers immediates Single cycle datapath CPI 1 CCT long 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Recap The MIPS Instruction Formats All MIPS instructions are 32 bits long The three instruction formats 31 op 6 bits R type I type 26 31 rs 5 bits 26 op 31 16 rt 5 bits 21 rs 6 bits J type 21 5 bits 11 rd 5 bits 6 shamt 5 bits 16 0 funct 6 bits 0 immediate rt 5 bits 16 bits 26 0 op 6 bits target address 26 bits The different fields are op operation of the instruction rs rt rd the source and destination registers specifier shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of the jump instruction 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Recap The MIPS Subset ADD and subtract add rd rs rt sub rd rs rt OR Imm ori rt rs imm16 31 26 op 6 bits 31 26 op 6 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 16 rt 5 bits 0 funct 6 bits 0 immediate 16 bits LOAD and STORE lw rt rs imm16 sw rt rs imm16 BRANCH beq rs rt imm16 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Recap A Single Cycle Datapath We have everything except control signals underline Today s lecture will show you how to generate the control signals 1 Mux 0 RegWr 5 5 Rs 5 Rt Rt ALUctr busA 0 1 32 2 22 99 ExtOp UCB Spring 1999 Clk Imm16 MemtoReg MemWr 0 32 Data In 32 ALUSrc Rd WrEn Adr 32 Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 ALU busW Zero Rs 0 15 Clk 11 15 RegDst Rt 16 20 Rd Instruction Fetch Unit 21 25 nPC sel Instruction 31 0 1 Data Memory CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topic Designing the Control for the Single Cycle Datapath 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Outline of Today s Lecture Recap and Introduction 10 minutes Control for Register Register Or Immediate instructions 10 minutes Questions and Administrative Matters 5 minutes Control signals for Load Store Branch Jump 15 minutes Building a local controller ALU Control 10 minutes Break 5 minutes The main controller 20 minutes Summary 5 minutes 2 22 99 UCB Spring 1999 CS152 Kubiatowicz RTL The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits add rd rs rt mem PC memory Fetch the instruction from R rd R rs R rt The actual operation PC PC 4 Calculate the next instruction s address 2 22 99 UCB Spring 1999 CS152 Kubiatowicz Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory Instruction mem PC This is the same for all instructions Inst Memory Instruction 31 0 Adr nPC sel 4 00 Adder imm16 PC Mux Adder PC Ext 2 22 99 Clk UCB Spring 1999 CS152 Kubiatowicz The Single Cycle Datapath during 26 21 16 11 Add 31 op rs rt rd Zero 32 2 22 99 ExtOp x UCB Spring 1999 Clk Imm16 MemtoReg 0 MemWr 0 0 32 Data In 32 ALUSrc 0 Rd WrEn Adr 32 Mux ALU 16 Extender imm16 1 Rs 0 15 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Rt 11 15 5 ALUctr Add Rt 16 20 5 Rs Instruction Fetch Unit Mux 32 Clk Clk 1 Mux 0 RegWr 1 5 busW Rt funct Instruction 31 0 21 25 RegDst 1 Rd 0 shamt R rd R rs R rt nPC sel 4 6 1 Data Memory CS152 Kubiatowicz Instruction Fetch Unit at the End of Add PC PC 4 This is the same for all instructions except Branch and Jump Inst Memory Instruction 31 0 Adr nPC sel Adder 0 imm16 PC Mux Adder 2 22 99 00 4 1 Clk UCB Spring 1999 CS152 Kubiatowicz The Single Cycle Datapath during Or 31 26 21 16 Immediate op rs rt 0 immediate R rt R rs or ZeroExt Imm16 Instruction 31 0 1 Mux 0 RegWr 5 5 Rs 5 Rt Rt ALUctr busA 0 1 32 2 22 99 ExtOp UCB Spring 1999 MemWr Clk Imm16 MemtoReg 0 32 Data In 32 ALUSrc Rd WrEn Adr 32 Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 ALU busW Zero Rs 0 15 Clk 11 15 Rt 21 25 RegDst Rd Instruction Fetch Unit 16 20 nPC sel 1 Data Memory CS152 Kubiatowicz The Single Cycle Datapath during 26 21 16 Load 31 op rs rt 0 immediate R rt Data Memory R rs SignExt imm16 Zero ALU 16 Extender imm16 1 32 2 22 99 ExtOp 1 UCB Spring 1999 Rd Imm16 MemtoReg 1 MemWr 0 0 32 Data In 32 ALUSrc 1 Rs Clk Mux busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Rt 0 15 5 ALUctr Add Rt 11 15 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr 1 5 busW Rt 16 20 RegDst 0 Rd Instruction Fetch Unit 21 25 nPC sel 4 Instruction 31 0 1 WrEn Adr Data Memory 32 CS152 Kubiatowicz Questions and Administrative Matters Tomorrow select groups for labs 4 7 Unbalanced sections Volunteers to come to afternoon If you don t come to section tomorrow you may end up in random group Midterm next Wednesday 3 3 5 30pm to 8 30pm 277 Cory Hall Make up quiz on Tuesday No class on that day Midterm reminders Pencil calculator two 8 5 x 11 pages of handwritten notes Sit in every other chair every other row odd row odd seat Meet at LaVal s pizza after the midterm Need a headcount How many are definitely coming 2 22 99 UCB Spring 1999 CS152 Kubiatowicz The Single Cycle Datapath during 26 21 16 Store 31 op rs rt immediate Data Memory R rs SignExt imm16 R rt 5 5 Rt Rt ALUctr busA 0 1 32 2 22 99 ExtOp UCB Spring 1999 MemWr Clk Imm16 MemtoReg 0 32 Data In 32 …
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